A3P015-1FG144 ACTEL [Actel Corporation], A3P015-1FG144 Datasheet - Page 105

• Manufacturer Part Number: A3P015-1FG144
• Description: ProASIC3 Flash Family FPGAs
• Manufacturer: ACTEL [Actel Corporation]

Table 2-107 • RAM4K9
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
F
Note:
AS
AH
ENS
ENH
BKS
BKH
DS
DH
CKQ1
CKQ2
WRO
CCKH
RSTBQ
REMRSTB
RECRSTB
MPWRSTB
CYC
MAX
For specific junction temperature and voltage supply levels, refer to
values.
Address setup time
Address hold time
REN_B, WEN_B setup time
REN_B, WEN_B hold time
BLK_B setup time
BLK_B hold time
Input data (DI) setup time
Input data (DI) hold time
Clock HIGH to new data valid on DO (output retained, WMODE = 0)
Clock HIGH to new data valid on DO (flow-through, WMODE = 1)
Clock HIGH to new data valid on DO (pipelined)
Address collision clk-to-clk delay for reliable read access after write
on same address
Address collision clk-to-clk delay for reliable write access after
write/read on same address
RESET_B LOW to data out LOW on DO (flow-through)
RESET_B LOW to Data Out LOW on DO (pipelined)
RESET_B removal
RESET_B recovery
RESET_B minimum pulse width
Clock cycle time
Maximum frequency
Timing Characteristics
Commercial-Case Conditions: T
Description
J
= 70°C, Worst-Case V
v1.3
CC
= 1.425 V
ProASIC3 DC and Switching Characteristics
Table 2-6 on page 2-6
0.25 0.28 0.33 0.40
0.00 0.00 0.00 0.00
0.14 0.16 0.19 0.23
0.10 0.11 0.13 0.16
0.23 0.27 0.31 0.37
0.02 0.02 0.02 0.03
0.18 0.21 0.25 0.29
0.00 0.00 0.00 0.00
2.36 2.68 3.15 3.79
1.79 2.03 2.39 2.87
0.89 1.02 1.20 1.44
TBD TBD TBD TBD
TBD TBD TBD TBD
0.92 1.05 1.23 1.48
0.92 1.05 1.23 1.48
0.29 0.33 0.38 0.46
1.50 1.71 2.01 2.41
0.21 0.24 0.29 0.34
3.23 3.68 4.32 5.19
310 272 231 193 MHz
–2
–1
Std.
for derating
–F
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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