A3P015-1FG144 ACTEL [Actel Corporation], A3P015-1FG144 Datasheet - Page 90
![no-image](/images/no-image-200.jpg)
A3P015-1FG144
Manufacturer Part Number
A3P015-1FG144
Description
ProASIC3 Flash Family FPGAs
Manufacturer
ACTEL [Actel Corporation]
Datasheet
1.A3P015-1FG144.pdf
(206 pages)
- Current page: 90 of 206
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ProASIC3 DC and Switching Characteristics
Table 2-96 • Combinatorial Cell Propagation Delays
2 -7 6
Combinatorial Cell
INV
AND2
NAND2
OR2
NOR2
XOR2
MAJ3
XOR3
MUX2
AND3
Note:
For specific junction temperature and voltage supply levels, refer to
values.
Timing Characteristics
VersaTile Specifications as a Sequential Module
The ProASIC3 library offers a wide variety of sequential cells, including flip-flops and latches. Each
has a data input and optional enable, clear, or preset. In this section, timing characteristics are
presented for a representative sample from the library. For more details, refer to the
IGLOO/e, and ProASIC3/E Macro Library
Figure 2-25 • Sample of Sequential Cells
Commercial-Case Conditions: T
Y = MAJ(A, B, C)
Y = A
Y = A !S + B S
Y = !(A + B)
Y = A · B · C
Y = !(A · B)
Y = A
Equation
Y = A + B
Y = A · B
Y = !A
Data
Data
CLK
CLK
CLR
B
B
C
D
D
DFN1C1
DFN1
J
Parameter
= 70°C, Worst-Case V
t
t
t
t
t
t
t
t
t
t
Q
Q
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
Guide.
v1.3
Out
Out
0.40
0.47
0.47
0.49
0.49
0.74
0.70
0.87
0.51
0.56
–2
CC
Data
Data
CLK
CLK
PRE
= 1.425 V
En
En
0.46
0.54
0.54
0.55
0.55
0.84
0.79
1.00
0.58
0.64
–1
D
D
Table 2-6 on page 2-6
DFI1E1P1
DFN1E1
0.54
0.63
0.63
0.65
0.65
0.99
0.93
1.17
0.68
0.75
Std.
Q
Q
Out
Out
0.65
0.76
0.76
0.78
0.78
1.19
1.12
1.41
0.81
0.90
–F
for derating
Units
Fusion,
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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