A3P015-1FG144 ACTEL [Actel Corporation], A3P015-1FG144 Datasheet - Page 75

• Manufacturer Part Number: A3P015-1FG144
• Description: ProASIC3 Flash Family FPGAs
• Manufacturer: ACTEL [Actel Corporation]

Figure 2-13 • LVPECL Circuit Diagram and Board-Level Implementation
Table 2-84 • Minimum and Maximum DC Input and Output Levels
Table 2-85 • AC Waveforms, Measuring Points, and Capacitive Loads
Table 2-86 • LVPECL
OUTBUF_LVPECL
DC Parameter
V
V
V
V
V
V
V
V
Input LOW (V)
1.64
*
Speed Grade
–F
Std.
–1
–2
Note:
CCI
OL
OH
IL
ODIFF
OCM
ICM
IDIFF
Measuring point = V
, V
IH
For specific junction temperature and voltage supply levels, refer to
values.
LVPECL
Low-Voltage Positive Emitter-Coupled Logic (LVPECL) is another differential I/O standard. It
requires that one data bit be carried through two signal lines. Like LVDS, two pins are needed. It
also requires external resistor termination.
The full implementation of the LVDS transmitter and receiver is shown in an example in
Figure
receiver macro, three board resistors at the transmitter end, and one resistor at the receiver end.
The values for the three driver resistors are different from those used in the LVDS implementation
because the output standard specifications are different.
Timing Characteristics
Commercial-Case Conditions: T
Supply Voltage
Output LOW Voltage
Output HIGH Voltage
Input LOW, Input HIGH Voltages
Differential Output Voltage
Output Common-Mode Voltage
Input Common-Mode Voltage
Input Differential Voltage
2-13. The building blocks of the LVPECL transmitter-receiver are one transmitter macro, one
FPGA
trip.
t
0.79
0.66
0.56
0.49
DOUT
See
Description
Table 2-22 on page 2-20
N
P
Bourns Part Number: CAT16-PC4F12
100
100
2.16
1.80
1.53
1.34
J
t
DP
= 70°C, Worst-Case V
Input HIGH (V)
187 W
1.94
v1.3
0.625
1.762
Min.
0.96
1.01
300
1.8
for a complete table of trip points.
0
Z
Z
0
0
3.0
= 50
= 50
Max.
1.27
2.11
0.97
1.98
2.57
0.05
0.04
0.04
0.03
3.3
t
DIN
CC
100
= 1.425 V, Worst-Case V
0.625
1.762
Min.
1.06
1.92
1.01
300
0
ProASIC3 DC and Switching Characteristics
3.3
Table 2-6 on page 2-6
N
P
Max.
1.43
2.28
0.97
1.98
2.57
3.6
1.69
1.40
1.19
1.05
Measuring Point* (V)
t
PY
FPGA
+
0.625
1.762
–
Min.
Cross point
1.30
2.13
1.01
300
0
3.6
CCI
INBUF_LVPECL
Max.
1.57
2.41
0.97
1.98
2.57
= 3.0 V
3.9
for derating
Units
ns
ns
ns
ns
Units
mV
V
V
V
V
V
V
V
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