A3P015-1FG144 ACTEL [Actel Corporation], A3P015-1FG144 Datasheet - Page 27

• Manufacturer Part Number: A3P015-1FG144
• Description: ProASIC3 Flash Family FPGAs
• Manufacturer: ACTEL [Actel Corporation]

1.
The PLL dynamic contribution depends on the input clock frequency, the number of output clock signals generated
by the PLL, and the frequency of each output clock. If a PLL is used to generate more than one output clock, include
each output clock in the formula by adding its corresponding contribution (P
contribution.
Combinatorial Cells Contribution—P
Routing Net Contribution—P
I/O Input Buffer Contribution—P
I/O Output Buffer Contribution—P
RAM Contribution—P
PLL Contribution—P
P
N
F
P
N
N
F
P
N
F
P
N
F
P
N
F
F
page
P
F
C-CELL
CLK
NET
CLK
INPUTS
CLK
OUTPUTS
CLK
MEMORY
READ-CLOCK
WRITE-CLOCK
PLL
CLKOUT
C-CELL
1
S-CELL
C-CELL
1
INPUTS
2
OUTPUTS
2
1
BLOCKS
2
3
is the toggle rate of VersaTile outputs—guidelines are provided in
is the toggle rate of VersaTile outputs—guidelines are provided in
is the I/O buffer toggle rate—guidelines are provided in
is the I/O buffer toggle rate—guidelines are provided in
is the I/O buffer enable rate—guidelines are provided in
is the RAM enable rate for read operations.
is the RAM enable rate for write operations—guidelines are provided in
= P
= (N
is the global clock signal frequency.
is the global clock signal frequency.
is the global clock signal frequency.
is the global clock signal frequency.
2-14.
= N
= N
DC4
is the number of VersaTiles used as sequential modules in the design.
is the number of VersaTiles used as combinatorial modules in the design.
is the number of VersaTiles used as combinatorial modules in the design.
is the number of I/O input buffers used in the design.
is the output clock frequency.
S-CELL
is the number of RAM blocks used in the design.
= N
= P
is the number of I/O output buffers used in the design.
C-CELL
INPUTS
+ P
AC11
OUTPUTS
is the memory read clock frequency.
is the memory write clock frequency.
AC13
+ N
*
*
* N
C-CELL
*F
1
PLL
2
*
BLOCKS
/ 2 * P
CLKOUT
MEMORY
/ 2 * P
) *
2
/ 2 *
AC7
* F
AC9
1
NET
/ 2 * P
READ-CLOCK
* F
* F
1
* P
CLK
INPUTS
CLK
AC8
AC10
OUTPUTS
C-CELL
v1.3
1
* F
*
* F
CLK
CLK
2
+ P
AC12
* N
BLOCK
ProASIC3 DC and Switching Characteristics
AC14
Table 2-16 on page
Table 2-16 on page
Table 2-17 on page
* F
* F
WRITE-CLOCK
CLKOUT
Table 2-16 on page
Table 2-16 on page
product) to the total PLL
*
3
2-14.
2-14.
2-14.
Table 2-17 on
2-14.
2-14.
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