OX16C950 OXFORD [Oxford Semiconductor], OX16C950 Datasheet - Page 19

• Manufacturer Part Number: OX16C950
• Description: High Performance UART with 128 byte FIFOs
• Manufacturer: OXFORD [Oxford Semiconductor]

7
7.1
After a hardware reset, all writable registers are reset to
0x00, with the following exceptions:
1. DLL which is reset to 0x01.
2. MCR[7] is reset to the complement of the CLKSEL
3. CPR is reset to 0x20.
The state of read-only registers following a hardware reset
is as follows:
RHR[7:0]: Indeterminate
RFL[6:0]: 0000000
TFL[6:0]: 0000000
LSR[7:0]: 0x60 signifying that both the transmitter and the
MSR[3:0]: 0000
MSR[7:4]: Dependent on modem input lines DCD, RI, DSR
ISR[7:0]: 0x01, i.e. no interrupts are pending
ASR[7:0]: 1xx00000
RFC[7:0]: 00000000
GDS[7:0]: 00000001
DMS[7:0]: 00000010
CKA[7:0]: 00000000
The reset state of output signals for are tabulated below:
Data Sheet Revision 1.2
RXRDY#
TXRDY#
OXFORD SEMICONDUCTOR LTD.
Signal
SOUT
RTS#
DTR#
input pin value (see section 11.1).
INT
R
Hardware Reset
ESET
transmitter FIFO are empty
and CTS respectively
Table 8: Output Signal Reset State
Inactive low when INTSEL# pin is high or
C
Active low (THR is able to receive data).
2
ONFIGURATION
floating, otherwise high-impedance
2
2
2
2
2
2
2
Inactive High
Inactive High
Inactive High
Inactive High
Reset state
7.2
An additional feature available in the OX16C950 device is
software resetting of the serial channel. The software reset
is available using the CSR register. Software reset has the
same effect as a hardware reset except it does not reset
the clock source selections (i.e. CKS register and CKA
register). To reset the UART write 0x00 to the Channel
Software Reset register ‘CSR’.
Software Reset
OX16C950 rev B
Page 19