ISP1130DL Philips Semiconductors, ISP1130DL Datasheet - Page 25

• Manufacturer Part Number: ISP1130DL
• Description: Universal Serial Bus compound hub with integrated keyboard controller
• Manufacturer: Philips Semiconductors

Table 25: Set Mode command, Configuration byte: bit allocation
Table 26: Set Mode command, Configuration byte: bit description
Philips Semiconductors
9397 750 06895
Objective specification
Bit
7
6
5
4
3
2
1
0
Bit
Symbol
Reset
Access
Symbol
-
ClockRestart
StringDescriptorEnable
RemoteWakeUpEnable
AlwaysPLLClock
UseIntDnResistor
-
InterruptOnNAK
W
X
7
-
9.1.3 Set Mode command
9.2.1 Read Interrupt Register command
9.2 Data flow commands
Selects the operating mode and (de)activates features. The command is followed by
one data write, containing the Configuration byte.
Code (Hex) — F3
Transaction — write 1 byte (Configuration).
Data flow commands are used to manage the data transmission between the USB
endpoints and the embedded microcontroller. Much of the data flow is initiated via an
interrupt to the microcontroller. The data flow commands are used to access the
endpoints and determine whether the endpoint FIFOs contain valid data.
Remark: The IN buffer of an endpoint contains input data for the host, the OUT buffer
receives output data from the host.
Shows the source(s) of an interrupt to the microcontroller. After writing the command,
two bytes are read which hold the interrupt register contents. Byte 1 contains the
least significant bits (7 to 0), byte 2 the most significant bits (15 to 8).
Code (Hex) — F4
Transaction — read 2 bytes.
Restart
Clock
W
6
0
Description
reserved
A logic 1 will cause a clock restart for 2 ms upon a bus transition, when the device
is in ‘suspend’ mode. This allows the device to wake up without resume signaling.
A logic 1 enables the string descriptor. The default string will be sent to the host
upon request.
A logic 1 enables remote wake-up by key press (embedded function 1).
A logic 1 indicates that the internal clocks and PLL are always running, even in
‘suspend’ mode. A logic 0 stops the internal clock, crystal oscillator and PLL.
A logic 1 causes the downstream pull-down resistors to be connected.
reserved; must always be logic 0
A logic 1 will generate an interrupt upon sending a NAK. A logic 0 will only report
successful transactions.
Descriptor
Enable
String
W
5
0
Rev. 01 — 23 March 2000
WakeUp
Remote
Enable
W
4
0
USB compound hub with keyboard controller
Always
Clock
PLL
W
3
0
Resistor
IntDn
Use
W
2
0
© Philips Electronics N.V. 2000. All rights reserved.
W
1
0
-
ISP1130
Interrupt
OnNAK
W
0
1
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