ISP1130DL Philips Semiconductors, ISP1130DL Datasheet - Page 46

• Manufacturer Part Number: ISP1130DL
• Description: Universal Serial Bus compound hub with integrated keyboard controller
• Manufacturer: Philips Semiconductors

11. I
Philips Semiconductors
9397 750 06895
Objective specification
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C-bus interface
10.11.2 Resume
Remark: After a resume operation, the microcontroller has to clear bit SuspendClock
to logic 0 to enable further suspend operations.
The ISP1130 can resume operation from ‘suspend’ state in three ways, depending on
whether the operating clocks are active or not:
A simple I
an external EEPROM upon a (power-on) reset or a bus reset from the USB host. The
interface hardware supports both single master and slave operation at bus speeds up
to 400 kHz.
For this application the user must configure the I
software. After reading the EEPROM configuration data, the I
module and the EEPROM must be disabled, since the SCL and SDA lines are
multiplexed with keyboard matrix scan lines (MX3 and MX4 respectively). Output
MEMSEL/UPGL is available for (de)selecting the EEPROM.
The I
serial bus wires, SDA (data) and SCL (clock). Both lines are driven by open-drain
circuits and must be connected to the positive supply voltage via pull-up resistors. In
the ISP1130 8.2 k pull-up resistors are integrated on pins MX3/SCL and MX4/SDA.
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SuspendClock = 0: The operating clocks of the USB core and the microcontroller
remain on during ‘suspend’ state. The device’s power consumption is not reduced
and therefore this state does not guarantee ‘suspend’ current requirements.
SuspendClock = 1: The internal clocks are automatically switched off after 2 ms.
This allows the microcontroller adequate time to process the ‘suspend’ interrupt
and enter Power-down mode. Power consumption is reduced to its minimum to
meet the ‘suspend’ current requirements of USB Specification Rev. 1.1 .
SuspendClock is changed from 0 to 1: The clocks are switched off after 1 ms.
This option can be used if the microcontroller requires more time than 2 ms to
prepare for ‘suspend’ mode.
Operating clock on: Clearing the Suspend bit of the Device Status Register to
logic 0 will generate a remote wake-up signal.
Operating clock off: The following events will generate a remote wake-up signal:
Upon a remote wake-up signal, the USB core first enables the PLL and the clocks.
When the clocks have stabilized, an interrupt wakes up the microcontroller from
Power-down mode. The microcontroller resumes program execution from where it
left off. A ‘resume’ signal is then generated on the upstream port.
– Key press (activity on the MYn lines)
– USB bus activity.
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C-bus interface is intended for bidirectional communication between ICs via two
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C-bus interface is provided in the ISP1130 to read configuration data from
Rev. 01 — 23 March 2000
USB compound hub with keyboard controller
2
C-bus interface as single master via
© Philips Electronics N.V. 2000. All rights reserved.
2
C-bus driver software
ISP1130
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