RD48F2000P0ZBQ0 Intel Corporation, RD48F2000P0ZBQ0 Datasheet - Page 20

• Manufacturer Part Number: RD48F2000P0ZBQ0
• Description: Intel StrataFlash Embedded Memory
• Manufacturer: Intel Corporation

1-Gbit P30 Family
4.2
Table 3.
April 2005
20
A[MAX:1]
DQ[15:0]
ADV#
CE#
CLK
OE#
RST#
WAIT
WE#
WP#
VPP
VCC
Symbol
Signal Descriptions
This section has signal descriptions for the various P30 packages.
TSOP and Easy BGA Signal Descriptions (Sheet 1 of 2)
Power/
Output
Output
Power
Input/
Type
Input
Input
Input
Input
Input
Input
Input
Input
Input
ADDRESS INPUTS: Device address inputs. 64-Mbit: A[22:1]; 128-Mbit: A[23:1]; 256-Mbit: A[24:1];
512-Mbit: A[25:1].
See
DATA INPUT/OUTPUTS: Inputs data and commands during write cycles; outputs data during
memory, Status Register, Protection Register, and Read Configuration Register reads. Data balls
float when the CE# or OE# are deasserted. Data is internally latched during writes.
ADDRESS VALID: Active low input. During synchronous read operations, addresses are latched on
the rising edge of ADV#, or on the next valid CLK edge with ADV# low, whichever occurs first.
In asynchronous mode, the address is latched when ADV# going high or continuously flows through
if ADV# is held low.
WARNING: Designs not using ADV# must tie it to VSS to allow addresses to flow through.
FLASH CHIP ENABLE: Active low input. CE# low selects the associated flash memory die. When
asserted, flash internal control logic, input buffers, decoders, and sense amplifiers are active. When
deasserted, the associated flash die is deselected, power is reduced to standby levels, data and
WAIT outputs are placed in high-Z state.
WARNING: All chip enables must be high when device is not in use.
CLOCK: Synchronizes the device with the system’s bus frequency in synchronous-read mode.
During synchronous read operations, addresses are latched on the rising edge of ADV#, or on the
next valid CLK edge with ADV# low, whichever occurs first.
WARNING: Designs not using CLK for synchronous read mode must tie it to VCCQ or VSS.
OUTPUT ENABLE: Active low input. OE# low enables the device’s output data buffers during read
cycles. OE# high places the data outputs and WAIT in High-Z.
RESET: Active low input. RST# resets internal automation and inhibits write operations. This
provides data protection during power transitions. RST# high enables normal operation. Exit from
reset places the device in asynchronous read array mode.
WAIT: Indicates data valid in synchronous array or non-array burst reads. Read Configuration
Register bit 10 (RCR[10], WT) determines its polarity when asserted. WAIT’s active output is V
V
WRITE ENABLE: Active low input. WE# controls writes to the device. Address and data are latched
on the rising edge of WE#.
WRITE PROTECT: Active low input. WP# low enables the lock-down mechanism. Blocks in lock-
down cannot be unlocked with the Unlock command. WP# high overrides the lock-down function
enabling blocks to be erased or programmed using software commands.
Erase and Program Power: A valid voltage on this pin allows erasing or programming. Memory
contents cannot be altered when V
should not be attempted.
Set V
from the system supply, the V
min to perform in-system flash modification. VPP may be 0 V during read operations.
V
cycles. VPP can be connected to 9 V for a cumulative total not to exceed 80 hours. Extended use of
this pin at 9 V may reduce block cycling capability.
Device Core Power Supply: Core (logic) source voltage. Writes to the flash array are inhibited when
V
• In synchronous array or non-array read modes, WAIT indicates invalid data when asserted and
• In asynchronous page mode, and all write modes, WAIT is deasserted.
OH
PPH
CC
valid data when deasserted.
Table 5 on page 22
when CE# and OE# are V
≤ V
PP
can be applied to main blocks for 1000 cycles maximum and to parameter blocks for 2500
LKO
= V
Intel StrataFlash
CC
. Operations at invalid V
Order Number: 306666, Revision: 001
for in-system program and erase operations. To accommodate resistor or diode drops
and
Figure 10 on page 23
IH
®
IL
level of V
Embedded Memory (P30)
. WAIT is high-Z if CE# or OE# is V
PP
CC
≤ V
voltages should not be attempted.
Name and Function
PP
PPLK
can be as low as V
. Block erase and program at invalid V
for 512-Mbit addressing.
PPL
min. V
IH
.
PP
must remain above V
PP
voltages
Datasheet
OL
PPL
or