RD48F2000P0ZBQ0 Intel Corporation, RD48F2000P0ZBQ0 Datasheet - Page 87

• Manufacturer Part Number: RD48F2000P0ZBQ0
• Description: Intel StrataFlash Embedded Memory
• Manufacturer: Intel Corporation

Figure 42.
Datasheet
Buffer Program Flowchart
Issue Buffer Prog. Cmd.
Read Status Register
Read Status Register
Buffer Program Data,
Start Word Address
Write Word Count,
Write Confirm 0xD0
Program Complete
and Word Address
at Word Address
Check if Desired
Supports Buffer
Target Address
Intel StrataFlash
Set Timeout or
Word Address
Word Address
Loop Counter
Write Buffer
Is BP finished?
Available?
Full Status
Get Next
(Note 7)
SR[7] =
(Note 5)
Device
Writes?
X = N?
0xE8,
X = 0
SR[7] =
Start
Order Number: 306666, Revision: 001
1 = Yes
1=Yes
Yes
Yes
0=No
0 = No
No
No
Buffer Program Aborted
®
Write Buffer Data,
Use Single Word
Write to another
Word Address
Block Address
Programming
Embedded Memory (P30)
Abort Buffer
Program?
X = X + 1
Expired?
No
or Count
Timeout
Program?
Suspend
No
Yes
Buffer Programming Procedure
No
Yes
Yes
Status Register
Issue Read
Command
Suspend
Program
Loop
1. Word count value on D[7:0] is loaded into the word count
register. Count ranges for this device are N = 0x00 to 0x1F.
2. The device outputs the Status Register when read.
3. Write Buffer contents will be programmed at the issued word
address.
4. Align the start address on a Write Buffer boundary for
maximum programming performance (i.e., A[4:0] of the Start
Word Address = 0x00).
5. The Buffered Programming Confirm command must be
issued to an address in the same block, for example, the
original Start Word Address, or the last address used during the
loop that loaded the buffer data.
6. The Status Register indicates an improper command
sequence if the Buffer Program command is aborted; use the
Clear Status Register command to clear error bits.
7. The Status Register can be read from any address within
the programming partition.
Full status check can be done after all erase and write
sequences complete. Write 0xFF after the last operation to
place the partition in the Read Array state.
(Notes 1, 2)
(Notes 3, 4)
(Notes 5, 6)
Operation
(Note 3)
Read
Read
Write
Write
Write
Write
Write
Bus
Idle
Idle
Buffer Prog.
Buffer Prog.
Command
Setup
None
None
None
None
None
Conf.
None
None
Data = 0xE8
Addr = Word Address
SR[7] = Valid
Addr = Word Address
Check SR[7]:
1 = Write Buffer available
0 = No Write Buffer available
Data = N-1 = Word Count
N = 0 corresponds to count = 1
Addr = Word Address
Data = Write Buffer Data
Addr = Start Word Address
Data = Write Buffer Data
Addr = Word Address
Data = 0xD0
Addr = Original Word Address
Status register Data
Addr = Note 7
Check SR[7]:
1 = WSM Ready
0 = WSM Busy
1-Gbit P30 Family
Comments
April 2005
87