RD48F2000P0ZBQ0 Intel Corporation, RD48F2000P0ZBQ0 Datasheet - Page 22
RD48F2000P0ZBQ0
Manufacturer Part Number
RD48F2000P0ZBQ0
Description
Intel StrataFlash Embedded Memory
Manufacturer
Intel Corporation
Datasheet
1.RD48F2000P0ZBQ0.pdf
(102 pages)
- Current page: 22 of 102
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1-Gbit P30 Family
Table 4.
4.3
Table 5.
Table 6.
April 2005
22
WP#
VPP
VCC
VCCQ
VSS
RFU
DU
NC
Symbol
QUAD+ SCSP Signal Descriptions (Sheet 2 of 2)
SCSP Configurations
Stacked Easy BGA Chip Select Logic
QUAD+ SCSP Chip Select Logic
Power/
Power
Power
Power
Type
Input
lnput
—
—
—
Combination
Stack Combination
Stack
1-die
2-die
4-die
WRITE PROTECT: Active low input. WP# low enables the lock-down mechanism. Blocks in lock-
down cannot be unlocked with the Unlock command. WP# high overrides the lock-down function
enabling blocks to be erased or programmed using software commands.
Erase and Program Power: A valid voltage on this pin allows erasing or programming. Memory
contents cannot be altered when V
should not be attempted.
Set V
from the system supply, the V
min to perform in-system flash modification. VPP may be 0 V during read operations.
V
cycles. VPP can be connected to 9 V for a cumulative total not to exceed 80 hours. Extended use of
this pin at 9 V may reduce block cycling capability.
Device Core Power Supply: Core (logic) source voltage. Writes to the flash array are inhibited when
V
Output Power Supply: Output-driver source voltage.
Ground: Connect to system ground. Do not float any VSS connection.
Reserved for Future Use: Reserved by Intel for future device functionality and enhancement. These
should be treated in the same way as a Do Not Use (DU) signal.
Do Not Use: Do not connect to any other signal, or power supply; must be left floating.
No Connect: No internal connection; can be driven or floated.
PPH
CC
1-die
2-die
≤ V
PP
can be applied to main blocks for 1000 cycles maximum and to parameter blocks for 2500
LKO
= V
Intel StrataFlash
CC
. Operations at invalid V
Order Number: 306666, Revision: 001
F1-CE# + A24 (V
F1-CE# + A24 (V
for in-system program and erase operations. To accommodate resistor or diode drops
Selected Flash
F1-CE#
Die #1
F1-CE# + A25 (V
IH
®
Selected Flash
IL
IL
level of V
Embedded Memory (P30)
)
)
F1-CE#
Die #1
PP
F1-CE# + A24 (V
F1-CE# + A24 (V
CC
Selected Flash
≤ V
voltages should not be attempted.
Name and Function
PP
PPLK
Die #2
can be as low as V
IL
-
. Block erase and program at invalid V
)
IH
IH
)
)
F2-CE# + A24 (V
F1-CE# + A25 (V
Selected Flash
Selected Flash
PPL
Die #3
min. V
Die #2
-
-
-
PP
must remain above V
IL
IH
)
)
F2-CE# + A24 (V
Selected Flash
PP
Die #4
voltages
Datasheet
-
-
PPL
IH
)
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