M36DR432BD ST Microelectronics, M36DR432BD Datasheet
M36DR432BD
Related parts for M36DR432BD
M36DR432BD Summary of contents
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... ACCESS TIMES: 85ns, 100ns, 120ns LOW POWER CONSUMPTION ELECTRONIC SIGNATURE – Manufacturer Code: 0020h – Top Device Code, M36DR432AD: 00A0h – Bottom Device Code, M36DR432BD: 00A1h FLASH MEMORY MEMORY BLOCKS – Dual Bank Memory Array: 4 Mbit, 28 Mbit – Parameter Blocks (Top or Bottom location) PROGRAMMING TIME – ...
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... M36DR432AD, M36DR432BD TABLE OF CONTENTS SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 3. TFBGA Connections (Top view through package SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Address Inputs (A0-A17 Address Inputs (A18-A20 Data Input/Output (DQ0-DQ15 Flash Chip Enable (EF Flash Output Enable (GF Flash Write Enable (WF Flash Write Protect (WPF) ...
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... Flash Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Data Polling Bit (DQ7 Toggle Bit (DQ6).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Toggle Bit (DQ2).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Error Bit (DQ5 Erase Timer Bit (DQ3 Polling and Toggle Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 11. Polling and Toggle Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 12. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 SRAM COMPONENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 SRAM Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 M36DR432AD, M36DR432BD 3/52 ...
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... M36DR432AD, M36DR432BD Standby/Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Data Retention Output Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 MAXIMUM RATING Table 13. Absolute Maximum Ratings( AND AC PARAMETERS Table 14. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 6. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 7. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 15. Device Capacitance Table 16. Flash DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 17. SRAM DC Characteristics (T Figure 8. Flash Random Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 9 ...
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... Table 27. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 APPENDIX A. BLOCK ADDRESSES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 28. Bank A, Top Boot Block Addresses M36DR432AD . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 29. Bank B, Top Boot Block Addresses M36DR432AD . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 30. Bank B, Bottom Boot Block Addresses M36DR432BD . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Table 31. Bank A, Bottom Boot Block Addresses M36DR432BD . . . . . . . . . . . . . . . . . . . . . . . . . . 47 APPENDIX B. COMMON FLASH INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Table 32. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Table 33 ...
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... M36DR432AD, M36DR432BD SUMMARY DESCRIPTION The M36DR432AD/ low-voltage Multiple Memory Product which combines two memory de- vices Mbit (2Mbit x16) non-volatile Flash memory and a 4 Mbit SRAM. The memory is available in a Stacked LFBGA66 12x8mm - 8x8 active ball array, 0.8mm pitch pack- age and supplied with all the bits erased (set to ‘ ...
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... Figure 3. TFBGA Connections (Top view through package) M36DR432AD, M36DR432BD 7/52 ...
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... M36DR432AD, M36DR432BD SIGNAL DESCRIPTIONS See Figure 2 Logic Diagram and Table 1, Signal Names, for a brief overview of the signals connect this device. Address Inputs (A0-A17). Addresses are common inputs for the Flash and the SRAM components. The Address Inputs select the cells in the memory array to access during Bus Read operations ...
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... WS is active Low. SRAM Output Enable (GS). The Output Enable gates the outputs through the data buffers during a read operation of the SRAM chip active Low. M36DR432AD, M36DR432BD SRAM Upper Byte Enable (UBS). Enables upper bytes for SRAM (DQ8-DQ15). UBS is active Low. and IL SRAM Lower Byte Enable (LBS) ...
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... M36DR432AD, M36DR432BD FUNCTIONAL DESCRIPTION The Flash and SRAM components have separate power supplies and grounds and are distinguished by three chip enable inputs: EF for the Flash mem- Figure 4. Functional Block Diagram RPF WPF A18-A20 A0-A17 E1S E2S GS WS UBS LBS 10/52 ory and ES (E1S and E2S, respectively) for the SRAM ...
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... M36DR432AD, M36DR432BD ( UBS, LBS SRAM must be disabled SRAM must be disabled SRAM must be disabled Any SRAM mode is allowed Any SRAM mode is allowed Any SRAM mode is allowed ...
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... Appendix A. The Parameter Blocks are located at the top of the memory address space for the M36DR432AD and, at the bottom for the M36DR432BD. Each block can be erased separately. Erase can be suspended, in order to perform either read or program in any other block, and then resumed. ...
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... Program or Erase must be monitored using an address within the bank being modified. Flash Command Interface All Bus Write operations to the memory are inter- preted by the Command Interface. Commands consist of one or more sequential Bus Write oper- ations. An internal Program/Erase Controller han- M36DR432AD, M36DR432BD AI06185 . IH and the P/E ...
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... M36DR432AD, M36DR432BD dles all timings and verifies the correct execution of the Program and Erase commands. Two bus write cycles are required to unlock the Command Interface. They are followed by a setup or confirm cycle. The increased number of write cycles is to ensure maximum data security. ...
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... Erase operations from changing the data in it. All blocks are locked at power-up or reset. Three Bus Write cycles are required to issue the Block Lock command. M36DR432AD, M36DR432BD The first two bus cycles unlock the Command Interface. The third bus cycle sets up the Block Lock command and latches the block address ...
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... M36DR432AD, M36DR432BD gram the block as the Program/Erase Controller does it automatically before erasing. Six Bus Write cycles are required to issue the command. The first two write cycles unlock the Command Interface. The third write cycles sets up the command the fourth and fifth write cycles repeat the unlock ...
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... Read until Toggle stops, then read all the data needed from any Blocks not being erased then Resume Erase. Read Data Polling or Toggle Bits until Erase completes or Erase is suspended PA C0h PA M36DR432AD, M36DR432BD 5th 6th Add Data Add Data Add Data command is issued. 03h ...
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... M36DR432AD, M36DR432BD Table 5. Read Electronic Signature Code Device Manufacturer Code M36DR432AD Device Code M36DR432BD Note Don’t care. Table 6. Flash Read Block Protection Block Status Locked Block IL IL Unlocked Block Locked-Down Block Note Don’t care. ...
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... The lock status is represented by DQ0 and DQ1. DQ0 indi- cates the Block Lock/Unlock status and is set by the Lock command and cleared by the Unlock command also automatically set when enter- M36DR432AD, M36DR432BD DQ7-3 DQ2 DQ1 Security ...
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... M36DR432AD, M36DR432BD ing Lock-Down. DQ1 indicates the Lock-Down sta- tus and is set by the Lock-Down command. It cannot be cleared by software, only by a hardware reset or power-down. The following sections explain the operation of the locking system. Locked State The default status of all blocks on power-up or af- ter a hardware reset is Locked (states (0,0,1) or (1,0,1)) ...
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... DQ2 will be set to '1' during program operation and to ‘0’ in erase operation read operation is addressed to a block where an erase error has occurred, DQ2 will toggle. M36DR432AD, M36DR432BD (1) After Block After Lock-Down WPF transition ...
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... M36DR432AD, M36DR432BD Error Bit (DQ5). The Error Bit can be used to identify if an error occurs during a program or erase operation. The Error Bit is set to ‘1’ when a program or erase operation has failed. When it is set to ‘0’ the pro- gram or erase operation was successful. ...
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... Erase Error due to the currently addressed block (when DQ5 = ’1’). Program in progress or Erase complete. Erase Suspend read on non Erase Suspend block. M36DR432AD, M36DR432BD Note Indicates the P/E.C. status, check during Program or Erase, and on completion before checking bits DQ5 for Program or Erase success. Successive reads output ...
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... M36DR432AD, M36DR432BD SRAM COMPONENT The SRAM Mbit (256Kb x16) low-power con- sumption memory array with low V tion. SRAM Operations The following operations can be performed using the appropriate bus cycles: Read Array, Write Ar- ray, Output Disable, Power Down (see Table 2). ...
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... DDF plied. Exposure to Absolute Maximum Rating con- ditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality docu- ments. (1) Parameter (3) M36DR432AD, M36DR432BD Value Unit – °C –40 to 125 °C –55 to 150 °C ...
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... M36DR432AD, M36DR432BD DC AND AC PARAMETERS This section summarizes the operating measure- ment conditions, and the DC and AC characteris- tics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed under the Measurement Table 14. Operating and AC Measurement Conditions Parameter ...
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... Bank V = 12V ± 0.6V PPF V V PPF 12V ± 0.6V PPF 100µ –100µ Double Word Program is don’t care. PPF M36DR432AD, M36DR432BD Min Typ Max ±1 ± 0.2 5 100 400 –0.5 0.4 – ...
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... M36DR432AD, M36DR432BD Table 17. SRAM DC Characteristics (T = –40 to 85° DDF DDS Symbol Parameter Output Leakage I OZ Current I Input Load Current IX V Standby DD I DDS Current I Supply Current DD V Input Low Voltage IL V Input High Voltage IH V Output Low Voltage OL V Output High Voltage ...
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... Figure 8. Flash Random Read AC Waveforms M36DR432AD, M36DR432BD 29/52 ...
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... M36DR432AD, M36DR432BD Figure 9. Flash Page Read AC Waveforms 30/52 ...
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... after the falling edge of EF without increasing t ELQV GLQV M36DR432AD, M36DR432BD M36DR432AD, M36DR432BD 85 100 Min Max Min Max Min (3) 100 120 85 (3) 100 85 ( (3) 100 ...
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... VALID tAVWL tELWL tGHWL tWLWH tDVWH Parameter 85 Min ( ( tWLAX tWHEH tWHGL tWHWL tWHDX VALID M36DR432AD, M36DR432BD 100 120 Max Min Max Min 100 120 ...
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... Parameter Min ( ( M36DR432AD, M36DR432BD tELAX tEHWH tEHGL tEHEL tEHDX VALID M36DR432AD, M36DR432BD 85 100 120 Max Min Max Min 100 120 ...
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... RPF Low to Reset t PLQ7V Complete t t RPF Pulse Width PLPH RP 34/52 READ VALID Test Condition Min During Program During Erase 50 PROGRAM / ERASE DQ7 VALID tPLPH tPLQ7V M36DR432AD, M36DR432BD 85 100 120 Max Min Max Min 150 150 AI07316 Unit Max 150 ...
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... Figure 13. Flash Data Polling DQ7 AC Waveforms M36DR432AD, M36DR432BD 35/52 ...
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... M36DR432AD, M36DR432BD Figure 14. Flash Data Toggle DQ6, DQ2 AC Waveforms 36/52 ...
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... START READ DQ5 & DQ7 at VALID ADDRESS DQ7 = DATA NO NO DQ5 = 1 YES READ DQ7 DQ7 = DATA NO FAIL Parameter Figure 16. Flash Data Toggle Flowchart YES YES PASS AI06197 M36DR432AD, M36DR432BD M36DR432AD, M36DR432BD Unit Min Max 8 100 0 100 0 100 0 100 0.8 4 ...
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... M36DR432AD, M36DR432BD Figure 17. SRAM Read Mode AC Waveforms, Address Controlled with UBS = LBS = V A0-A17 DQ0-DQ15 DATA VALID Note Low Low High. Figure 18. SRAM Read AC Waveforms Controlled A0-A17 ES UBS, LBS GS DQ0-DQ15 Note: Write Enable (WS) = High. 38/52 tAVAV VALID tAVQV tAXQX tAVAV VALID tAVQV ...
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... GLQV Output Enable Low to Output Transition GLQX OLZ (1) Chip Enable High to Power Down t PD (1) Chip Enable Low to Power Note: 1. Sampled only. Not 100% tested. tPU Parameter M36DR432AD, M36DR432BD tPD AI07320 SRAM 70 Unit Min Max ...
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... M36DR432AD, M36DR432BD Figure 20. SRAM Write AC Waveforms, WS Controlled with GS Low A0-A17 tAVEL ES UBS, LBS tAVWL WS tWLQZ DQ0-DQ15 Note: Output Enable (GS) = Low. Figure 21. SRAM Write AC Waveforms, WS Controlled with GS High A0-A17 tAVEL ES UBS, LBS tAVWL WS GS DQ0-DQ15 40/52 tAVAV VALID tAVWH tELWH tBLWH tWLWH tDVWH ...
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... DQ0-DQ15 Figure 23. SRAM Write AC Waveforms, ES Controlled A0-A17 ES UBS, LBS WS DQ0-DQ15 Note: Output Enable (GS) = High. tAVAV VALID tAVWH tBLWH tWLEH tWLQZ tDVWH tAVAV VALID tAVEL tELWH tBLWH tWLWH tDVWH M36DR432AD, M36DR432BD tEHAX tWHQX tWHDX INPUT VALID tEHAX tWHDX INPUT VALID AI07323 AI07324 41/52 ...
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... M36DR432AD, M36DR432BD Table 24. SRAM Write AC Characteristics Symbol Alt t t Write Cycle Time AVAV WC (1) t Address Valid to Chip Enable Low t AVEL Address Valid to Write Enable High AVWH AW (1) t Address Valid to Write Enable Low t AVWL UBS, LBS Valid to End of Write BLWH ...
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... Note: 1. All other Inputs V V – 0. DDS 2. Sampled only. Not 100% tested. (1, 2) Test Condition V = 1.0V DDS DDS no input may exceed V DDS ES V – 0.2V DDS ES V – 0.2V DDS 0.2V. IL M36DR432AD, M36DR432BD Min Typical Max – 0. Unit µ 43/52 ...
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... M36DR432AD, M36DR432BD PACKAGE MECHANICAL Figure 25. Stacked LFBGA 12x8mm - 8x8 ball array, 0.8mm pitch, Bottom View Package Outline BALL "A1" Note: Drawing is not to scale. Table 26. Stacked LFBGA 12x8mm - 8x8 ball array, 0.8mm pitch, Package Mechanical Data Symbol Typ A A1 ...
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... Devices are shipped from the factory with the memory content bits erased to ’1’. For a list of available op- tions (Speed, Package, etc.) or for further information on any aspect of this device, please contact the ST- Microelectronics Sales Office nearest to you. M36DR432AD, M36DR432BD M36 32A ...
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... M36DR432AD, M36DR432BD APPENDIX A. BLOCK ADDRESSES Table 28. Bank A, Top Boot Block Addresses M36DR432AD Size # Address Range (KWord 1FF000h-1FFFFFh 13 4 1FE000h-1FEFFFh 12 4 1FD000h-1FDFFFh 11 4 1FC000h-1FCFFFh 10 4 1FB000h-1FBFFFh 9 4 1FA000h-1FAFFFh 8 4 1F9000h-1F9FFFh 7 4 1F8000h-1F8FFFh 6 32 1F0000h-1F7FFFh 5 32 1E8000h-1EFFFFh 4 32 1E0000h-1E7FFFh 3 32 1D8000h-1DFFFFh 2 32 ...
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... Table 31. Bank A, Bottom Boot Block Addresses M36DR432BD Size # Address Range (KWord 038000h-03FFFFh 13 32 030000h-037FFFh 12 32 028000h-02FFFFh 11 32 020000h-027FFFh 10 32 018000h-01FFFFh 9 32 010000h-017FFFh 8 32 008000h-00FFFFh ...
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... M36DR432AD, M36DR432BD APPENDIX B. COMMON FLASH INTERFACE The Common Flash Interface is a JEDEC ap- proved, standardized data structure that can be read from the Flash memory device. It allows a system software to query the device to determine various electrical and timing parameters, density information and functions supported by the mem- ory ...
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... HEX value in volts bit BCD value in 100 millivolts Note: This value must be 0000h times typical (offset 1Fh) n times typical (offset 22h) M36DR432AD, M36DR432BD pin is present PPF pin is present PPF n µs n µs n times typical (offset 20h) n times typical (offset 21h) ...
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... M36DR432AD, M36DR432BD Table 35. Device Geometry Definition Offset Word Data Mode 27h 0016h 28h 0001h 29h 0000h 2Ah 0000h 2Bh 0000h 2Ch 0002h M36DR432AD M36DR432AD Erase Block Region Information 2Dh 003Eh 2Eh 0000h 2Fh 0000h 30h 0001h 31h 0007h 32h 0000h 33h ...
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... Document promoted from Preliminary Data to full Datasheet status. V and V 28-Feb-2003 2.1 Measurement Conditions. V Revision Details signal removed from datasheet. SRAM Input Rise and Fall Times added to, DDQF and V parameters differentiated in Table 14, Operating and AC DDF DDS added to the SIGNAL DESCRIPTIONS section. DDS M36DR432AD, M36DR432BD 51/52 ...
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... M36DR432AD, M36DR432BD Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice ...