AT17LV002 ATMEL Corporation, AT17LV002 Datasheet - Page 23

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AT17LV002

Manufacturer Part Number
AT17LV002
Description
FPGA Configuration EEPROM Memory
Manufacturer
ATMEL Corporation
Datasheet

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44J – PLCC
2321E–CNFG–06/03
Notes:
R
2325 Orchard Parkway
San Jose, CA 95131
1. This package conforms to JEDEC reference MS-018, Variation AC.
2. Dimensions D1 and E1 do not include mold protrusion.
3. Lead coplanarity is 0.004" (0.102 mm) maximum.
0.51(0.020)MAX
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
45˚ MAX (3X)
1.14(0.045) X 45˚
B
e
TITLE
44J, 44-lead, Plastic J-leaded Chip Carrier (PLCC)
D1
D
PIN NO. 1
IDENTIFIER
AT17LV65/128/256/512/010/002/040
E1
1.14(0.045) X 45˚
E
SYMBOL
D2/E2
A
A1
A2
D
D1
E
E1
B
B1
e
A
17.399
16.510
17.399
16.510
14.986
4.191
2.286
0.660
0.330
0.508
COMMON DIMENSIONS
MIN
(Unit of Measure = mm)
B1
A2
A1
0.318(0.0125)
0.191(0.0075)
1.270 TYP
NOM
D2/E2
DRAWING NO.
17.653
16.662
17.653
16.662
16.002
4.572
3.048
0.813
MAX
0.533
44J
Note 2
Note 2
NOTE
10/04/01
REV.
B
23

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