AT17LV002 ATMEL Corporation, AT17LV002 Datasheet - Page 6

• Manufacturer Part Number: AT17LV002
• Description: FPGA Configuration EEPROM Memory
• Manufacturer: ATMEL Corporation

Pin Description
DATA
CLK
WP1
RESET/OE
WP
WP2
6
RESET/OE
SER_EN
READY
Name
DATA
WP1
WP2
GND
CEO
CLK
V
CE
A2
CC
AT17LV65/128/256/512/010/002/040
I/O
O
O
O
I/
I
I
I
I
I
I
I
SOIC
LAP/
DIP/
8
1
2
–
3
4
5
6
–
7
8
AT17LV128/
AT17LV256
AT17LV65/
PLCC
20
10
14
17
20
2
4
–
6
8
–
Three-state DATA output for configuration. Open-collector bi-directional pin for
programming.
Clock input. Used to increment the internal address and bit counter for reading and
programming.
WRITE PROTECT (1). Used to protect portions of memory during programming. Dis-
abled by default due to internal pull-down resistor. This input pin is not used during
FPGA loading operations. This pin is only available on AT17LV512/010/002 devices.
Output Enable (active High) and RESET (active Low) when SER_EN is High. A Low
level on RESET/OE resets both the address and bit counters. A High level (with CE
Low) enables the data output driver. The logic polarity of this input is programmable as
either RESET/OE or RESET/OE. For most applications, RESET should be programmed
active Low. This document describes the pin as RESET/OE.
Write protect (WP) input (when CE is Low) during programming only (SER_EN Low).
When WP is Low, the entire memory can be written. When WP is enabled (High), the
lowest block of the memory cannot be written. This pin is only available on
AT17LV65/128/256 devices.
WRITE PROTECT (2). Used to protect portions of memory during programming. Dis-
abled by default due to internal pull-down resistor. This input pin is not used during
FPGA loading operations. This pin is only available on AT17LV512/010 devices.
SOIC
20
10
14
17
20
2
4
–
6
8
–
DIP/
LAP
8
1
2
–
3
–
4
5
6
–
7
8
AT17LV512/
AT17LV010
PLCC
20
10
14
15
17
20
2
4
5
6
7
8
SOIC
20
10
11
13
18
20
1
3
–
8
–
–
–
SOIC
LAP/
DIP/
8
1
2
–
3
–
4
5
6
–
7
8
PLCC
20
10
14
15
17
20
2
4
5
6
7
8
AT17LV002
SOIC
20
10
11
13
18
20
1
3
–
8
–
–
–
PLCC
44
19
21
24
27
29
41
44
2
5
–
–
TQFP
44
40
43
13
15
18
21
23
35
38
–
–
2321E–CNFG–06/03
PLCC
44
AT17LV040
19
21
24
27
29
41
44
2
5
–
–
TQFP
44
40
43
13
15
18
21
23
35
38
–
–