TC94A04AFG Toshiba Semiconductor, TC94A04AFG Datasheet - Page 11

• Manufacturer Part Number: TC94A04AFG
• Description: 1 CHIP AUDIO DIGITAL PROCESSOR
• Manufacturer: Toshiba Semiconductor

2.2
2.2.1 Setting Registers
IFCK
IFDI
CS
(MCU → )
I
The IFDI signal is the data.
sent after that are fixed to two bytes. Both command and data are sent starting from the MSB in I
format.
the SYNC signal, such as the RUN command (command-44h) or the IFF flag (command-4Ah), must be
synchronized with the SYNC signal and loaded on that signal.
2
C Bus Mode
When I2CS = “H”, data can be transmitted or received in I
When the CS signal is Low, control from the microcontroller is enabled.
In I
The TC94A04AFG/AFDG loads the IFDI data on the IFCK signal rising edge.
When CS = “H”, IFCK and IFD signal are don't care.
The registers are set by command data using the IFDI signal.
The first byte after the I
The data loaded internally every two bytes. Note that commands or data that must be switched on
start
2
A7
C mode, the CS signal can be used fixed to “L”. The IFCK signal is the transmit/receive clock.
A6
A5
A4
32h
A3
A2
A1
A0
HZ
2
C7
C address ( = 32h) is a command, which differs for each register. The data
C6
C5
C4
C3
C2
C1
C0
HZ
11
D15
D14
D13
D12
D11
D10
D9
2
D8
C bus mode.
HZ
D7
D6
TC94A04AFG/AFDG
D5
D4
D3
D2
An: I
Cn: COMMAND
Dn: Data
HZ
2
C address
2005-09-28
end
2
C