TC94A04AFG Toshiba Semiconductor, TC94A04AFG Datasheet - Page 8

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TC94A04AFG

Manufacturer Part Number
TC94A04AFG
Description
1 CHIP AUDIO DIGITAL PROCESSOR
Manufacturer
Toshiba Semiconductor
Datasheet
2. Microcontroller Interface
2.1
2.1.1 Setting Resisters
Standard Transmission Mode
rising edge.
two bytes. Both command and data are sent starting from the MSB.
switched, such as the RUN-MUTE command (command-44h) or the IFF flag (command-4Ah), must be
synchronized with the SYNC signal and loaded on that signal.
When I2CS = “L”, data can be transmitted or received in Standard Transmission mode.
When the CS signal is Low, control from the microcontroller is enabled.
The IFCK signal is the transmit/receive clock.
The IFDI signal is the data. The TC94A04AFG/AFDG loads the IFDI signal on the IFCK signal
When CS = “H”, the IFCK and IFDI signals are don’t care.
The registers are set by command using the IFDI signals.
The first byte is a command, which differs for each register. The data sent after that are fixed to
Data are loaded the rising edge of the IFCK signal. Note that commands or data that must be
IFCK
IFDI
CS
Don’t care
C7
C6
C5
C4
C3
C2
C1
C0
D15
D14
D13
D12
8
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
Cn: COMMAND
Dn: Data
D0
TC94A04AFG/AFDG
Don’t care
2005-09-28

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