MCF5232 ETC, MCF5232 Datasheet - Page 51

• Manufacturer Part Number: MCF5232
• Description: Integrated Microprocessor Hardware Specification
• Manufacturer: ETC

Figure 19
6.10.2 MII Transmit Signal Timing (ETXD[3:0], ETXEN,
Table 38
The transmitter functions correctly up to a ETXCLK maximum frequency of 25 MHz +1%. There is no
minimum frequency requirement. In addition, the processor clock frequency must exceed twice the
ETXCLK frequency.
The transmit outputs (ETXD[3:0], ETXEN, ETXER) can be programmed to transition from either the
rising or falling edge of ETXCLK, and the timing is the same in either case. This options allows the use
of non-compliant MII PHYs.
Refer to the Ethernet chapter for details of this option and how to enable it.
Freescale Semiconductor
Num
M5
M6
M7
M8
Num
M1
M2
M3
M4
lists MII transmit channel timings.
shows MII receive signal timings listed in
ETXER, ETXCLK)
ETXCLK to ETXD[3:0], ETXEN, ETXER invalid
ETXCLK to ETXD[3:0], ETXEN, ETXER valid
ETXCLK pulse width high
ETXCLK pulse width low
ERXD[3:0] (inputs)
ERXD[3:0], ERXDV, ERXER to ERXCLK setup
ERXCLK to ERXD[3:0], ERXDV, ERXER hold
ERXCLK pulse width high
ERXCLK pulse width low
ERXCLK (input)
ERXDV
ERXER
MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3
Figure 19. MII Receive Signal Timing Diagram
Characteristic
Characteristic
Table 38. MII Transmit Signal Timing
Table 37. MII Receive Signal Timing
M1
Preliminary
M2
M3
Table
37.
35%
35%
Min
—
35%
35%
M4
5
Min
5
5
Preliminary Electrical Characteristics
Max
65%
65%
25
—
65%
65%
Max
—
—
ERXCLK period
ERXCLK period
ETXCLK period
ETXCLK period
Unit
Unit
ns
ns
ns
ns
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