MCF5232 ETC, MCF5232 Datasheet - Page 52

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MCF5232

Manufacturer Part Number
MCF5232
Description
Integrated Microprocessor Hardware Specification
Manufacturer
ETC
Datasheet

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Preliminary Electrical Characteristics
Figure 20
6.10.3 MII Async Inputs Signal Timing (ECRS and ECOL)
Table 39
Figure 21
6.10.4 MII Serial Management Channel Timing (EMDIO and EMDC)
Table 40
MDC frequency of 2.5 MHz.
52
Num
M9
Num
M10 EMDC falling edge to EMDIO output invalid (minimum propagation
M11 EMDC falling edge to EMDIO output valid (max prop delay)
M12 EMDIO (input) to EMDC rising edge setup
M13 EMDIO (input) to EMDC rising edge hold
M14 EMDC pulse width high
M15 EMDC pulse width low
lists MII asynchronous inputs signal timing.
lists MII serial management channel timings. The FEC functions correctly with a maximum
shows MII transmit signal timings listed in
shows MII asynchronous input timings listed in
ETXD[3:0] (outputs)
ECRS, ECOL minimum pulse width
ETXCLK (input)
delay)
ETXEN
ETXER
ECRS, ECOL
MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3
Table 40. MII Serial Management Channel Timing
Figure 20. MII Transmit Signal Timing Diagram
Figure 21. MII Async Inputs Timing Diagram
Characteristic
Table 39. MII Async Inputs Signal Timing
Characteristic
M5
M6
Preliminary
M7
Table
M9
Table
38.
39.
M8
Min
1.5
40% 60% MDC period
40% 60% MDC period
Min
10
0
0
Max
Max
25
Freescale Semiconductor
ETXCLK period
Unit
ns
ns
ns
ns
Unit

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