M306V5EESP Mitsubishi, M306V5EESP Datasheet - Page 135

• Manufacturer Part Number: M306V5EESP
• Description: SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
• Manufacturer: Mitsubishi

Rev. 1.0
(11) Example of Master Transmission
(12) Example of Slave Reception
An example of master transmission in the standard clock mode, at the SCL frequency of 100 kHz and
in the ACK return mode is shown below.
An example of slave reception in the high-speed clock mode, at the SCL frequency of 400 kHz, in the
ACK non-return mode, using the addressing format, is shown below.
•When all transmitted address are“0” (general call):
•When the transmitted addresses match the address set in
•In the cases other than the above:
register and set “0” in the least significant bit.
and an ACK clock automatically occurs.
occurs.
condition will be generated.
Set a slave address in the high-order 7 bits of the I
Set the ACK return mode and SCL = 100 kHz by setting “85
Set “10
Set a communication enable status by setting “08
Set the address data of the destination of transmission in the high-order 7 bits of the I
Set “F0
Set transmit data in the I
When transmitting control data of more than 1 byte, repeat step
Set “D0
Set a slave address in the high-order 7 bits of the I
Set the no ACK clock mode and SCL = 400 kHz by setting “25
Set “10
Set a communication enable status by setting “08
When a START condition is received, an address comparison is made.
AD0 of the I
ASS of the I
AD0 and AAS of the I
Set dummy data in the I
When receiving control data of more than 1 byte, repeat step
When a STOP condition is detected, the communication ends.
16
16
16
16
” in the I
” in the I
” in the I
” in the I
2
2
Ci status register is set to “1”and an interrupt request signal occurs.
Ci status register is set to “1” and an interrupt request signal occurs.
2
2
2
2
Ci status register and hold the SCL at the HIGH.
Ci status register to generate a START condition. At this time, an SCL for 1 byte
Ci status register. After this, if ACK is not returned or transmission ends, a STOP
Ci status register and hold the SCL at the HIGH.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
2
Ci status register are set to “0” and no interrupt request signal occurs.
2
2
Ci data shift register.
Ci data shift register. At this time, an SCL and an ACK clock automatically
16
16
2
2
” in the I
” in the I
Ci address register and “0” in the RBW bit.
Ci address register and “0” in the RBW bit.
:
2
2
16
Ci control register.
Ci control register.
and ON-SCREEN DISPLAY CONTROLLER
” in the I
16
.
” in the I
MITSUBISHI MICROCOMPUTERS
.
M306V5ME-XXXSP
2
Ci clock control register.
2
Ci clock control register.
M306V5EESP
2
Ci data shift
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