MC9328MX1/D ETC, MC9328MX1/D Datasheet - Page 24

• Manufacturer Part Number: MC9328MX1/D
• Description: i.MX Integrated Portable System Processor
• Manufacturer: ETC

Specifications
3.9.1 DTACK Signal Description
The DTACK signal is the external input data acknowledge signal. When using the external DTACK signal as a
data acknowledge signal, the bus time-out monitor generates a bus error when a bus cycle is not terminated by the
external DTACK signal after 1022 HCLK counts have elapsed. Only the CS5 group supports DTACK signal
function when the external DTACK signal is used for data acknowledgement.
3.9.2 DTACK Signal Timing
Figure 6 through Figure 9 show the access cycle timing used by chip-select 5. The signal values and units of
measure for this figure are found in the associated tables.
3.9.2.1 DTACK READ Cycle without DMA
24
Number
Databus
(input to MX1)
1
2
3
4
EB
CS5
OE
Address
Table 14. Parameters for Read Cycle, WSC = 111111, DTACK_SEL=0, HKCL=96MHz
DTACK
OE and EB assertion time
CS5 pulse width
OE negated to address inactive
DTACK asserted after CS5 asserted
(1)
Characteristic
programmable
min 0ns
(4)
Figure 6. DTACK READ Cycle without DMA
MC9328MX1 Advance Information, Rev. 4
(2)
(5)
(10)
(7)
See note 2
Minimum
46.44
3T
–
(3.0 ± 0.3) V
(9)
(6)
(8)
Maximum
1019T
(3)
Freescale Semiconductor
–
–
–
Unit
ns
ns
ns
ns