MC9328MX1/D ETC, MC9328MX1/D Datasheet - Page 54

• Manufacturer Part Number: MC9328MX1/D
• Description: i.MX Integrated Portable System Processor
• Manufacturer: ETC

Specifications
54
•
•
•
•
•
•
VSYN, HSYN and SCLK can be programmed as active high or active low. In the above timing diagram, all
these 3 signals are active high.
Ts is the shift clock period.
Ts = Tpix * (panel data bus width).
Tpix is the pixel clock period which equals LCDC_CLK period * (PCD + 1).
Maximum frequency of LCDC_CLK is 48 MHz, which is controlled by Peripheral Clock Divider Register.
Maximum frequency of SCLK is HCLK / 5, otherwise LD output will be wrong.
MC9328MX1 Advance Information, Rev. 4
Freescale Semiconductor