MC9328MX1/D ETC, MC9328MX1/D Datasheet - Page 28

• Manufacturer Part Number: MC9328MX1/D
• Description: i.MX Integrated Portable System Processor
• Manufacturer: ETC

Specifications
3.9.2.4 DTACK Write Cycle DMA Enabled
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Table 16. Parameters for Write Cycle WSC = 111111, DTACK_SEL=0, HKCL=96MHz (Continued)
Note:
0. DTACK assert mean DTACK become low.
1. T is the system clock period. (For 96MHz system clock)
2. CS5 assertion can be controlled by CSA bits. EB assertion can also be programmed by WEA bits in the CS5L register.
3. Address becomes valid and RW asserts at the start of write access cycle.
4. The external DTACK input requirement is eliminated when CS5 is programmed to use internal wait state.
Number
Number
Databus
(output from MX1)
RW
OE
1
2
3
4
5
6
EB
CS5
Address
Table 17. Parameters for Write Cycle WSC = 111111, DTACK_SEL=0, HCLK=96MHz
(logic high)
DTACK
EB assertion time
CS5 pulse width
RW negated before CS5 is negated
Address inactive before CS negated
CS5 assertion time
DTACK asserted after CS5 asserted
(1)
(2)
Characteristic
Characteristic
(9)
programmable
min 0ns
programmable
min 0ns
Figure 9. DTACK Write Cycle DMA Enabled
(6)
MC9328MX1 Advance Information, Rev. 4
(3)
(12)
(7)
See note 2
See note 2
1.5T+0.58
Minimum
Minimum
3T
–
–
(3.0 ± 0.3) V
(3.0 ± 0.3) V
(5)
(8)
(4)
(11)
Maximum
1.5T+1.58
Maximum
1019T
0.93
–
–
–
(10)
Freescale Semiconductor
Unit
Unit
ns
ns
ns
ns
ns
ns