UPD17073 NEC, UPD17073 Datasheet - Page 67
UPD17073
Manufacturer Part Number
UPD17073
Description
4-BIT SINGLE-CHIP MICROCONTROLLER WITH HARDWARE FOR DIGITAL TUNING SYSTEM
Manufacturer
NEC
Datasheet
1.UPD17073.pdf
(226 pages)
- Current page: 67 of 226
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11.2 Interrupt Control Block
absence of an interrupt request, enables/disables the interrupt, and generates a vector address when the interrupt
is accepted.
11.2.1 Interrupt request flag (IRQxxx)
peripheral hardware, and is cleared (0) when the interrupt has been accepted.
by checking these interrupt request flags.
to the flag by an instruction.
request that has not been accepted is not cleared.
At
INT pin
interrupt request
register
The interrupt request flags are set to (1) when an interrupt request has been issued from the corresponding
Therefore, even when the interrupt is not enabled, whether an interrupt request has been issued can be detected
Writing “1” directly to an interrupt request flag is equivalent to issuance of an interrupt request.
Once this flag has been set, it will not be cleared until the corresponding interrupt has been accepted, or “0” is written
If two or more interrupt requests are issued at the same time, the interrupt request flag corresponding to the interrupt
The interrupt request flags are address 58H through 5AH of BANK1 of RAM.
Figures 11-2 through 11-4 show the configuration and functions of each interrupt request register.
An interrupt control block is available for each peripheral hardware. Each of these blocks detects the presence/
Power-ON
Clock stop
CE
Name
0
b
0
Figure 11-2. Configuration of INT Pin Interrupt Request Register
3
Flag symbol
0
b
0
2
0
b
0
1
b
R
Q
0
0
0
0
1
I
0
Interrupt request not issued.
Interrupt request issued.
Fixed to "0".
(BANK1)
Address
58H
Read/
Write
R/W
Sets interrupt request issuing status of INT pin.
PD17072,17073
67
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