K4S161622D-TI/E10 Samsung semiconductor, K4S161622D-TI/E10 Datasheet - Page 7

• Manufacturer Part Number: K4S161622D-TI/E10
• Description: 1M x 16 SDRAM
• Manufacturer: Samsung semiconductor

K4S161622D-TI/E
AC OPERATING TEST CONDITIONS
Note :
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Notes :
CAS Latency
CLK cycle time
Row active to row active delay
RAS to CAS delay
Row precharge time
Row active time
Row cycle time
Last data in to row precharge
Last data in to new col.address delay
Last data in to burst stop
Col. address to col. address delay
Mode Register Set cycle time
Number of valid output
data
Input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
Output
1. The DC/AC Test Output Load of K4S161622D-50/55/60/70 is 30pF.
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then
(Fig. 1) DC Output Load Circuit
rounding off to the next higher integer. Refer to the following clock unit based AC conversion table
Parameter
870Ω
Parameter
CAS Latency=3
CAS Latency=2
3.3V
1200Ω
50pF
t
t
t
t
t
Symbol
t
t
t
t
RAS(max)
t
t
RRD(min)
RCD(min)
t
CCD(min)
MRS(min)
RAS(min)
RDL(min)
CDL(min)
BDL(min)
RC
*2
CC(min)
RP(min)
CL
(
min
V
V
)
OH
OL
(DC) = 0.4V, I
(V
(DC) = 2.4V, I
11
3
5
3
3
8
DD
-50
= 3.3V±0.3V
10
10
2
3
3
7
5.5
10
3
3
3
7
OL
OH
-55
= 2mA
= -2mA
*2
10
10
2
3
3
7
, Extended T
10
3
6
3
3
7
tr / tf = 1 / 1
See Fig. 2
-60
2.4 / 0.4
Value
1.4
1.4
Version
10
Output
2
2
2
5
7
100
A
2
1
1
1
1
2
2
1
= -25 to +85°C , Industrial T
10
3
7
3
3
7
-70
10
(Fig. 2) AC Output Load Circuit
2
2
2
5
7
3
8
3
3
6
9
-80
Z0=50Ω
10
2
2
2
5
7
CMOS SDRAM
Rev 1.2 Jan '03
10
3
2
2
5
7
-10
A
= -40 to +85°C)
12
2
2
2
4
6
Vtt=1.4V
Unit
50Ω
50pF
Unit
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
ns
V
V
V
ea
ns
us
*1
Note
2, 5
1
1
1
1
1
2
2
4