K4S161622D-TI/E10 Samsung semiconductor, K4S161622D-TI/E10 Datasheet - Page 8

• Manufacturer Part Number: K4S161622D-TI/E10
• Description: 1M x 16 SDRAM
• Manufacturer: Samsung semiconductor

K4S161622D-TI/E
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
5. Also, supported tRDL=2CLK for - 60 part which is distinguished by bucket code "J".
AC CHARACTERISTICS
Note :
CLK cycle time
CLK to valid
output delay
Output data
CLK high pulse
width
CLK low pulse
width
Input setup time
Input hold time
CLK to output in Low-Z
CLK to output
in Hi-Z
CLK cycle time
Row active to row active delay t
RAS to CAS delay
Row precharge time
Row active time
Row cycle time
From the next generation, tRDL will be only 2CLK for every clock frequency.
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf)=1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
Parameter
Parameter
CAS Latency=3
CAS Latency=2
CAS Latency=3
CAS Latency=2
CAS Latency=3
CAS Latency=2
CAS Latency=3
CAS Latency=2
CAS Latency=3
CAS Latency=2
CAS Latency=3
CAS Latency=2
t
t
t
t
t
t
CC(min)
RRD(min)
RCD(min)
RP(min)
RAS(min)
RAS(max)
RC
(AC operating conditions unless otherwise noted)
Symbol
Symbol
(
min
t
t
t
t
t
t
SAC
t
t
t
SHZ
SLZ
OH
CC
CH
SS
SH
CL
)
Min
1.5
10
5
2
2
3
2
3
2
1
1
-
-
-
-
-50
-50
10
15
15
40
55
5
1000
Max
4.5
4.5
6
6
-
-
-
-
-
-
Min
5.5
1.5
2
2
3
2
3
2
1
1
-
-
-
-
-
16.5
16.5
38.5
-55
-55
5.5
55
11
1000
Max
5
6
5
6
-
-
-
-
-
-
Min
2.5
2.5
2.5
1.5
6
3
3
2
1
1
-
-
-
-
-
-60
12
18
18
42
60
-60
6
1000
Max
5.5
5.5
Version
6
6
-
-
-
-
-
-
100
1.75
Min
2.5
10
7
3
3
2
1
1
-
-
-
-
-70
14
20
20
49
69
-70
7
1000
Max
5.5
5.5
6
6
-
-
-
-
-
-
Min
2.5
10
8
3
3
2
1
1
-
-
-
-
-80
16
20
20
48
70
-80
8
1000
Max
6
6
6
6
-
-
-
-
-
-
CMOS SDRAM
Rev 1.2 Jan '03
Min
2.5
3.5
3.5
2.5
10
12
1
1
-
-
-
-
-10
10
20
20
20
48
70
-10
1000
Max
6
8
6
8
-
-
-
-
-
-
Unit Note
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
ns
ns
ns
ns
ns
us
ns
1, 2
1
2
3
3
3
3
2