HYS64-74V8200GU Siemens, HYS64-74V8200GU Datasheet - Page 10
HYS64-74V8200GU
Manufacturer Part Number
HYS64-74V8200GU
Description
3.3 V 8M x 64/72-Bit 1 Bank SDRAM Module 3.3 V 16M x 64/72-Bit 2 Bank SDRAM Module
Manufacturer
Siemens
Datasheet
1.HYS64-74V8200GU.pdf
(17 pages)
AC Characteristics (cont’d)
T
Parameter
Refresh Cycle
Refresh Period
(4096 cycles)
Self Refresh Exit Time
Read Cycle
Data Out Hold Time
Data Out to Low Impedance
Data Out to High Impedance
DQM Data Out Disable
Latency
Write Cycle
Data input to Precharge
(write recovery)
Data In to Active/Refresh
DQM Write Mask Latency
Semiconductor Group
A
= 0 to 70 C;
V
SS
= 0 V;
V
CC
3, 4
Symbol
t
t
t
t
t
t
t
t
t
REF
SREX
OH
LZ
HZ
DQZ
DPL
DAL
DQW
= 3.3 V
–
10
3
0
3
–
2
5
0
0.3 V,
min. max. min. max. min. max.
PC100-222
-8
10
t
64
–
–
–
8
2
–
–
–
T
= 1 ns
HYS 64(72)V8200/16220GU-8/-10
Limit Values
–
10
3
0
3
–
2
5
0
PC100-323
-8B
64
–
–
–
10
2
–
–
–
–
10
3
0
3
–
2
5
0
PC66
-10
SDRAM Modules
64
–
–
–
10
2
–
–
–
Unit
ms
ns
ns
ns
ns
CLK
CLK
CLK
CLK
1998-08-01
Note
8
9
4
10