HYS64-74V8200GU Siemens, HYS64-74V8200GU Datasheet - Page 9

• Manufacturer Part Number: HYS64-74V8200GU
• Description: 3.3 V 8M x 64/72-Bit 1 Bank SDRAM Module 3.3 V 16M x 64/72-Bit 2 Bank SDRAM Module
• Manufacturer: Siemens

AC Characteristics
T
Parameter
Clock and Clock Enable
Clock Cycle Time
System Frequency
Clock Access Time
Clock High Pulse Width
Clock Low Pulse Width
Input Setup Time
Input Hold Time
CKE Setup Time
(Power down mode)
CKE Setup Time
(Self Refresh Exit)
Transition Time
(rise and fall)
Common Parameters
RAS to CAS delay
Precharge Time
Active Command Period
Cycle Time
Bank to Bank Delay Time
CAS to CAS Delay Time
(same bank)
Semiconductor Group
A
= 0 to 70 C;
CAS Latency = 3
CAS Latency = 2
CAS Latency = 3
CAS Latency = 2
CAS Latency = 3
CAS Latency = 2
V
SS
= 0 V;
3, 4
V
CC
Symbol
t
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
CK
CK
AC
CH
CL
CS
CH
CKSP
CKSR
T
RCD
RP
RAS
RC
RRD
CCD
= 3.3 V
10
10
–
–
–
–
3
3
2
1
2.5
8
1
20
20
50
70
16
1
0.3 V,
min. max. min. max. min. max.
PC100-222
-8
t
–
–
100
100
6
6
–
–
–
–
–
–
–
–
–
100k 60
–
–
–
9
T
= 1 ns
HYS 64(72)V8200/16220GU-8/-10
Limit Values
10
12
–
–
–
–
3
3
2
1
2.5
10
1
20
30
80
20
1
PC100-323
-8B
–
–
100
83
6
7
–
–
–
–
–
–
–
–
–
100k 70
–
–
–
10
15
–
–
–
–
3.5
3.5
3
1
3
8
1
30
30
80
20
1
PC66
-10
SDRAM Modules
–
–
100
66
8
9
–
–
–
–
–
–
–
–
–
100k ns
–
–
–
Unit
ns
ns
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CLK
1998-08-01
Note
4, 5
6
6
7
7
8
9