HYS64-74V8200GU Siemens, HYS64-74V8200GU Datasheet - Page 16

• Manufacturer Part Number: HYS64-74V8200GU
• Description: 3.3 V 8M x 64/72-Bit 1 Bank SDRAM Module 3.3 V 16M x 64/72-Bit 2 Bank SDRAM Module
• Manufacturer: Siemens

SPD-Table for PC66 Modules (cont’d)
Byte# Description
22
23
24
25
26
27
28
29
30
31
32
33
34
35
62-61 Superset information
62
63
64-
125
126
127
128+
Semiconductor Group
SDRAM Device Attributes:
General
Min. Clock Cycle Time at
CAS Latency = 2
Max. data access time from
Clock for CL= 2
Minimum Clock Cycle Time
at CL = 1
Maximum Data Access
Time from Clock at CL = 1
Minimum Row Precharge
Time
Minimum Row Active to
Row Active delay
Minimum RAS to CAS delay
t
Minimum RAS pulse width
t
Module Bank Density (per
bank)
SDRAM input setup time
SDRAM input hold time
SDRAM data input hold time 3 ns
SDRAM data input setup
time
(may be used in future)
SPD Revision
Checksum for bytes 0 - 62
Manufacturers information
(optional)
(FF
Frequency Specification
Details
Unused storage locations
RCD
RAS
H
if not used)
t
RRD
SPD Entry Value
V
15.0 ns
9.0 ns
not supported
not supported
30 ns
20 ns
30 ns
45 ns
64 MByte
3 ns
1 ns
1 ns
Revision 1.2
66 MHz
CC
tol
10%
16
HYS 64(72)V8200/16220GU-8/-10
06
F0
90
FF
FF
1E
14
1E
2D
10
30
10
30
10
FF
12
B0
XX
66
AF
FF
8M 64
-10
06
F0
90
FF
FF
1E
14
1E
2D
10
30
10
30
10
FF
12
C2
XX
66
AF
FF
8M 72
-10
SDRAM Modules
Hex
06
F0
90
FF
FF
1E
14
1E
2D
10
30
10
30
10
FF
12
B1
XX
66
FF
FF
16M 64
-10
1998-08-01
16M 72
06
F0
90
FF
FF
1E
14
1E
2D
10
30
10
30
10
FF
12
C3
XX
66
FF
FF
-10