S2021B AMCC (Applied Micro Circuits Corp), S2021B Datasheet

S2021B

Manufacturer Part Number

S2021B

Description

Manufacturer

AMCC (Applied Micro Circuits Corp)

Datasheet

1.S2021B.pdf (23 pages)

Specifications of S2021B

Case

QFP

Date_code

08+

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Company:

Bonase Electronics (HK) Co., Limited

Part Number:

S2021B

Manufacturer:

AMCC

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885

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DEVICE SPECIFICATION

FEATURES

Figure 1. Interface Signal Summary

HIPPI SOURCE/DESTINATION INTERFACE CIRCUITS

• Functionally compliant with the ANSI HIPPI

• 32-Bit data channel

• Equivalent single channel rate of 800 Mbits/sec

• Host-side interface single-ended TTL designed

• Channel-side interface differential ECL 10K

• Four rank data and control signal

• Byte parity checking

• Length/Longitudinal Redundancy Checkword

• Automatic division of data into HIPPI bursts

• 16-Bit READY counter for flow control

• Maximum latency through both ICs

• Diagnostic modes for self test

• Standard +5V, 0V(gnd), and -5.2V power

• 225-pin ceramic PGA package

• 208-pin Thermally Enhanced Plastic (TEP)

Source: ANSI X3.183–1991

standard

for use with external FIFO

synchronization

(LLRC) generation and checking

Connection: 600ns, Data: 400ns

requirements

Source

High-Performance Parallel Interface.

Mechanical, Electrical, and Signalling

Protocol Specification (HIPPI-PH).

Request

Connect

Data Bus

Parity Bus

Ready

Packet

Burst

Clock

Interconnect S

Interconnect D

Destination

GENERAL DESCRIPTION

The S2020 and the S2021 are Source and Destination

interface circuits, respectively, for the High-

Performance Parallel Interface (HIPPI) standard.

These circuits are designed to completely meet the

signalling protocol of the proposed ANSI HIPPI

specification: current document number X3.183–

1991 They include both LLRC generation and

checking as well as byte parity checking. The

S2021 also incorporates a sophisticated four rank

synchronization scheme to ensure that the incoming

data and control signals are coupled to the local

clock. Data flow control is provided by a 16-bit ready

counter in both the Source and the Destination

circuits. HIPPI data BURST partitioning is also

provided in the Source circuit.

Architected and designed by Network Systems

Corporation, the S2020 and S2021 utilize AMCC’s

1.5-micron BiCMOS technology. AMCC’s BiCMOS

technology is especially optimized for high performance

mixed mode ECL/TTL applications such as the

HIPPI Source and Destination interfaces. AMCC

pioneered ECL/TTL mixed mode BiCMOS capability

and continues to be the leading U.S. supplier of

BiCMOS VLSI circuits.

S2020/S2021 HIPPI Chipset

S2020/S2021

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