IA186EM-PQF100I-R INNOVASIC [InnovASIC, Inc], IA186EM-PQF100I-R Datasheet - Page 15

• Manufacturer Part Number: IA186EM-PQF100I-R
• Description: 8/16-Bit Microcontrollers
• Manufacturer: INNOVASIC [InnovASIC, Inc]

IA186EM/IA188EM
8/16-BIT Microcontrollers
D0DSTL (0c4h)
The sixteen bits of these registers are combined with the four bits of the respective DMA Destination
Address High Register to produce a 20-bit destination address.
The D0DSTL and D1DSTL registers are undefined at reset.
D1SRCH (0d2h) - DMA SouRCe Address High Register.
D0SRCH (0c2h)
The 20-bit source address consists of these four bits combined with the 16-bits of the respective Source
Address Low Register. A DMA transfer requires that two complete 16-bit registers in the peripheral
control block (high and low registers) be used for both the source and destination addresses of each DMA
channel involved. Each DMA channel requires that all four address registers be initialized. Each address
may be incremented or decremented independently of the other after each transfer. The addresses are
incremented or decremented by 2 for word transfers and incremented or decremented by 1 for byte
transfers.
The D0SRCH and D1SRCHL registers are undefined at reset.
D1SRCL (0d0h) - DMA SouRCe Address Low Register.
D0SRCL (0c0h)
The sixteen bits of these registers are combined with the four bits of the respective DMA Source Address
High register to produce a 20-bit source address.
The D0SRCL and D1SRCL registers are undefined at reset.
DDA [15:0] (bits 15-0) – DMA Destination Address Low bits are driven onto A15-A0 during the
write phase of a DMA transfer.
Reserved [15:4] (bits 15-4) – Reserved
DSA [19:16] (bits 3-0) – DMA Source Address High bits are driven onto A19-A16 during the read
phase of a DMA transfer.
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14
14
14
13
13
13
12
12
12
Reserved
11
11
11
DDA15 – DDA0
DSA15-DSA0
10
10
10
As of Production Version -03
9
9
9
8
8
8
7 6 5 4 3
7 6 5 4 3
7 6 5 4 3
DSA19 –DSA16
2
2
2
Data Sheet
1
1
1
0
0
0