IA186EM-PQF100I-R INNOVASIC [InnovASIC, Inc], IA186EM-PQF100I-R Datasheet - Page 47

• Manufacturer Part Number: IA186EM-PQF100I-R
• Description: 8/16-Bit Microcontrollers
• Manufacturer: INNOVASIC [InnovASIC, Inc]

IA186EM/IA188EM
8/16-BIT Microcontrollers
This register controls the operation of the sden1 and sden0 outputs and the baud rate of the SSI port. The
sden1 and sden0 outputs are held high when the respective bit is set to 1, but in the event that both DE1
and DE0 are set to 1 then only sden0 will be held high.
The value of the SSR register is 0000h at reset.
SSS (010h) – Synchronous Serial Status Register.
This is a read only register that indicates the state of the SSI port.
The value of the SSR register is 0000h at reset.
Reserved (bits 15-6) – Reserved Bits.
SCLKDIV (bits 5-4) – SCLK Divide. These bits set the SCLK frequency. SCLK is the result of
dividing the internal processor clock by 2, 4, 8, or 16 as in the following table.
RES (bits 3-2) – Reserved Bits.
DE1 (bit1) - SDEN1. The SDEN1 bit is held high when this bit is set to 1 and SDEN1 is held low
when this bit is set to 0.
DE0 (bit0) – SDEN0. The SDEN0 bit is held high when this bit is set to 1 and SDEN0 is held low
when this bit is set to 0.
Reserved (bits 15-3) – Reserved Bits.
RE/TE (bit 2) – Receive/Transmit Error Detect. This bit is set to 1 when a read of the Synchronous
Serial Received register or a write to one of the transmit register is detected while the interface is busy
15
15
3737 Princeton NE, Ste 130 • Albuquerque, NM 87107 • Tel [phone] • Fax [phone] • www.Innovasic.com
14
14
13
13
12
12
11
Reserved
11
SCLKDIV
10
Reserved
10
00b
01b
10b
11b
9
9
8
SCLK Frequency Divider
Processor Clock /2
Processor Clock /4
Processor Clock /8
Processor Clock /16
8
7
7
As of Production Version -03
6
6
5
SCLKDIV
5
4
4
3
RE/TE DR/DT PB
3
RES
2
2
Data Sheet
1
DE1-DE0
1
0
0