IA186EM-PQF100I-R INNOVASIC [InnovASIC, Inc], IA186EM-PQF100I-R Datasheet - Page 39

• Manufacturer Part Number: IA186EM-PQF100I-R
• Description: 8/16-Bit Microcontrollers
• Manufacturer: INNOVASIC [InnovASIC, Inc]

IA186EM/IA188EM
8/16-BIT Microcontrollers
REQST (02eh) – Interrupt REQueST Register.
Master Mode
This is a read-only register and such a read results in the status of the interrupt request bits presented to
the interrupt controller.
The REQST register is undefined on reset.
DHLT (bit 15) – DMA Halt. DMA activity is halted when this bit is 1. It is set to 1 automatically
when any non-maskable interrupt occurs and is cleared to 0 when an IRET instruction is executed.
Reserved (bits 14-3)
TMR [2:0] (bit 2-0) – Timer Interrupt Request. A pending interrupt request is indicated by the
respective timer, when any of these bits is 1. (N.B. the TMR bit in the REQST register is a logical OR
of these timer interrupt requests.)
Reserved (bits 15 – 11)
SPI (bit 10) – Serial Port Interrupt Request. This is the serial port interrupt state and when enabled is
the logical OR of all the serial port 0 interrupt sources: - THRE, RDR, BRKI, FER, PER, and OER.
WD (bit 9) – Watchdog Timer Interrupt Request. This is the watchdog interrupt state and indicates
that an interrupt is pending when it is a 1.
I [4:0] (bits 8 - 4) Interrupt Requests. Setting any of these bits to 1 indicates that the relevant
interrupt has a pending interrupt.
D1-D0 (bit 3:2) DMA Channel Interrupt 6 Request. Setting either bit to 1 indicates that either the
respective DMA channel has a pending interrupt.
Reserved (bit 1)
TMR (bit 0) – Timer Interrupt Request. This is the timer interrupt state and is the logical OR of the
timer interrupt requests. Setting this bit to 1 indicates that the timer control unit has a pending
interrupt.
DHLT
15
15
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14
14
Reserved
13
13
12
12
11
11
SPI WD I4 I3 I2 I1 IO
10
10
Reserved
9
9
8
8
7
As of Production Version -03
7
6
6
5
5
4
4
3
D1- D0
3
2
2
TMR2 - TMR0
Res
1
1
Data Sheet
TMR
0
0