IA186EM-PQF100I-R INNOVASIC [InnovASIC, Inc], IA186EM-PQF100I-R Datasheet - Page 58

no-image

IA186EM-PQF100I-R

Manufacturer Part Number
IA186EM-PQF100I-R
Description
8/16-Bit Microcontrollers
Manufacturer
INNOVASIC [InnovASIC, Inc]
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IA186EM-PQF100I-R-03
Manufacturer:
INNOVASIC
Quantity:
3 590
Part Number:
IA186EM-PQF100I-R-03
Manufacturer:
Innovasic Semiconductor
Quantity:
10 000
IA186EM/IA188EM
8/16-BIT Microcontrollers
Asynchronous Serial Port
The asynchronous serial port employs standard industry communication protocols in its implementation
of full duplex, bi-directional data transfers. The port can be the source or destination of DMA transfers.
The following features are supported:
" Full-duplex data transfers
" 7-, 8-, or 9-bit data transfers
" Odd, even, or no parity
" One or two stop bits
" Error detection provided by Parity, Framing, or Overrun errors
" Hardware handshaking is achieved with the following selectable control signals: Clear-to-send (cts_n)
"
"
"
"
"
In power-save mode the baud rate generator divide factor must be re-programmed to compensate for the
change in clock rate.
Synchronous Serial Port
The synchronous serial port allows the microcontrollers to communicate with ASICs that are required to
be programmed but have a pin shortage. The four-pin interface allows half-duplex, bi-directional data
transfer at a maximum of 20 Mbits/sec with a 40 MHz CPU clock.
The synchronous serial interface of the AI186EM/AI188EM operates as the master port in a master/slave
arrangement.
There are four pins in the synchronous serial interface for communication with the system elements.
These pins are two enables (SDEN0 and SDEN1), a clock (SCLK) and a data pin (SDATA).
In power-save mode, the baud rate generator divide factor must be re-programmed to compensate for the
change in clock rate.
DMA to and from the port
The port has its own maskable interrupt
The port has an independent baud rate generator
Maximum baud rate is 1/32 of the processor clock
Transmit and Receive lines are double buffered
o Enable receiver request (enrx_n)
o Ready to send (rts_n)
o Ready to receive (rtr_n)
3737 Princeton NE, Ste 130 • Albuquerque, NM 87107 • Tel 505.883.5263 • Fax 505.883.5477 • www.Innovasic.com
As of Production Version -03
Data Sheet

Related parts for IA186EM-PQF100I-R