73K324L-IGT ETC [List of Unclassifed Manufacturers], 73K324L-IGT Datasheet

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73K324L-IGT

Manufacturer Part Number
73K324L-IGT
Description
CCITT V.22bis, V.22, V.21, V.23, Bell 212A Single-Chip Modem
Manufacturer
ETC [List of Unclassifed Manufacturers]
Datasheet
DESCRIPTION
The 73K324L is a highly integrated single-chip
modem IC which provides the functions needed to
design
compatible modem capable of operation over dial-up
lines. The 73K324L adds V.23 capability to the
CCITT modes of TDK Semiconductor Corporation's
73K224 one-chip modem, allowing a one-chip
implementation in designs intended for European
markets which require this added Modulation mode.
The 73K324L offers excellent performance and a
high level of functional integration in a single IC. The
device supports V.22bis, V.22, Bell 212A, V.21, and
V.23 operating modes, allowing both synchronous
and asynchronous operation as defined by the
appropriate standard.
The 73K324L is designed to appear to the Systems
Engineer as a microprocessor peripheral, and will
easily
microcontrollers
modem functions through its 8-bit multiplexed
address/data bus. A serial control bus is available
for applications not requiring a parallel interface. An
optional package with only the serial control bus is
also available. Data communications occurs through
a separate serial port.
BLOCK DIAGRAM
a
RXD
TXD
interface
Quad-mode
SERIAL
8 - BIT
m
BUS
I/F
I/F
P
(80C51
with
CCITT
typical)
DEBUFFER
BUFFER
popular
and
for
SCRAMBLER
SCRAMBLER
DE-
Bell
control
CCITT V.22bis, V.22, V.21, V.23, Bell 212A
(continued)
one-chip
DECODER
QUADBIT
DIBIT/
212A
ENCODER
QUADBIT
DIBIT/
of
MODULATOR
TONE DETECTION
PROCESSOR
FSK
FUNCTIONS
RECEIVE
SHAPER
DIGITAL
PULSE
SIGNAL
FIR
FEATURES
One chip Multi-mode CCITT V.22bis, V.22, V.21,
V.23 and Bell 212A compatible modem data pump
FSK (75, 300, 1200 bit/s), DPSK (600, 1200 bit/s),
or QAM (2400 bit/s) encoding
Pin and software compatible with other
TDK Semiconductor Corporation K-Series family
one-chip modems
Interfaces directly with standard
microprocessors (8048, 80C51 typical)
Serial and parallel microprocessor bus for
control
Selectable asynch/synch with internal
buffer/debuffer and scrambler/descrambler
functions
All synchronous (internal, external, slave) and
Asynchronous Operating modes
Adaptive equalization for optimum performance
over all lines
Programmable transmit attenuation (16 dB, 1 dB
steps), and selectable receive boost (+18 dB)
Call progress, carrier, answer tone, unscrambled
mark, S1, and signal quality monitors
DTMF, answer, calling, SCT and guard tone
generators
Test modes available: ALB, DL, RDL; Mark, Space
and Alternating bit pattern generators
CMOS technology for low power consumption
(100 MW @ 5 V) with power-down mode
(15 mW @ 5V)
4-wire full duplex operation in all modes
MODULATOR
A/D
DPSK
QAM/
FILTER
DEMOD
FIXED
+
GENERATOR
EQUALIZER
ANSWER,
GUARD &
CALLING
DTMF,
TONE
EQUALIZER
AGC
Single-Chip Modem
6 dB
GAIN
BOOST
FILTER
FILTER
+
ATTEN
6 dB
GAIN BOOST
FILTER
73K324L
FILTER
April 2000
RXA
TXA

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73K324L-IGT Summary of contents

Page 1

... IC. The device supports V.22bis, V.22, Bell 212A, V.21, and V.23 operating modes, allowing both synchronous and asynchronous operation as defined by the appropriate standard. The 73K324L is designed to appear to the Systems Engineer as a microprocessor peripheral, and will easily interface with popular ...

Page 2

... Semiconductor's K-Series family modems, allowing system upgrades with a single component change. The 73K324L is ideal for use in free-standing or integral system modem products where full-duplex 2400 bit/s operation with Alternate mode capability is required. Its high functionality, low power consumption, and efficient packaging simplify design requirements and increase system reliability ...

Page 3

... SERIAL CONTROL INTERFACE The Serial Command mode allows access to the 73K324L control and status registers via a serial and synchronous control port. In this mode the A0, A1, and A2 lines provide register addresses for data passed through the DATA pin under control of the RD and WR lines ...

Page 4

... VDD Write. A low on this informs the 73K324L that data is available on AD0-AD7 for writing into an internal register. Data is latched on the rising edge of WR. No data is written unless both WR and the latched CS are low. The Serial Control mode is provided by tying ALE high and CS low. In this configuration AD7 becomes NOTE: DATA and AD0, AD1 and AD2 become the address only ...

Page 5

... These pins are for the internal crystal oscillator requiring a 11.0592 MHz Parallel mode crystal. Two capacitors from these pins to ground are also required for XTL2 I/O proper crystal operation. Consult crystal manufacturer for proper values. XTL2 can also be driven from an external clock. CCITT V.22bis, V.22, V.21, V.23, Bell 212A 5 73K324L Single-Chip Modem ...

Page 6

... AD0, AD1 and AD2 lines in Parallel mode. The address lines are latched by ALE. Register CR0 controls the method by which data is transferred over the phone line. CR1 controls the interface between the microprocessor and the 73K324L REGISTER BIT SUMMARY ADDRESS REGISTER ...

Page 7

... TRANSMIT TRANSMIT ATTEN. ATTEN. ATTEN. ATTEN 0000-1111, SETS TRANSMIT ATTENUATOR 16 dB RANGE DEFAULT=0100 ³ -10 dbM0 TXD SOURCE SELECT1 SELECT0 0=TXD PIN 1=TX DATA -5 00³10 BER CR3-D7 -6 01³10 BER -4 10³10 BER -3 11³10 BER 73K324L ...

Page 8

... CCITT V.22bis, V.22, V.21, V.23, Bell 212A Single-Chip Modem CONTROL REGISTER CR0 MODUL. MODUL. 000 OPTION TYPE 1 BIT NO. NAME D0 Answer/ Originate D1 Transmit Enable D5, D4, Transmit D3, D2 Mode MODUL. TRANSMIT TRANSMIT TYPE 0 MODE 2 MODE 1 CONDITION DESCRIPTION 0 Selects Answer mode (transmit in high band, receive in low band ...

Page 9

... CR3 bit D2. The output of the clock pin will be set to the crystal frequency. 0 Selects 11.0592 MHz crystal echo output at CLK pin. 1 Selects 16 X the data rate output at CLK pin in QAM and DPSK only. 9 73K324L Single-Chip Modem RESET TEST TEST MODE ...

Page 10

... CCITT V.22bis, V.22, V.21, V.23, Bell 212A Single-Chip Modem CONTROL REGISTER 1 (continued TRANSMIT TRANSMIT CR1 PATTERN PATTERN 001 1 0 BIT NO. NAME D4 Bypass Scrambler/ Add Ph. Eq. D5 Enable Detect Interrupt D7, D6 Transmit Pattern ENABLE BYPASS CLK CONTROL DETECT SCRAMB/ INT. ADD PH.EQ. CONDITION DESCRIPTION 0 Selects normal operation ...

Page 11

... Received signal level below threshold, ( -25 dBm0);can use receive gain boost (+18 dB) 1 Received signal above threshold. 11 Single-Chip Modem SPECIAL CALL TONE PROG. DETECT DETECT unscrambled 73K324L D0 SIGNAL QUALITY INDICATOR double dibit ...

Page 12

... CCITT V.22bis, V.22, V.21, V.23, Bell 212A Single-Chip Modem TONE REGISTER D7 D6 RXD TRANSMIT TR OUTPUT GUARD/ 011 CONTR. CALLING/SCT TONE BIT NO. NAME D0, D4, D5, D6 DTMF 0/Guard Tone/Answer Tone/Calling/ SCT Tone/ Transmit Select D1 DTMF 1/ Overspeed D2 DTMF 2/ 4 WIRE FDX NOTE: DTMF0 - DTMF2 should be set to an appropriate state after DTMF dialing to avoid unintended operation ...

Page 13

... Enables RXD pin. Receive data will be output on RXD. 1 Disables RXD pin. The RXD pin reverts to a high impedance with internal weak pull-up resistor. 13 73K324L Single-Chip Modem DTMF 2/ DTMF 1/ DTMF 0/ WIRE OVER- GUARD/ FDX SPEED CALLING/SCT TONE SEL ...

Page 14

... CCITT V.22bis, V.22, V.21, V.23, Bell 212A Single-Chip Modem CONTROL REGISTER SPEC CR2 REG 100 ACCESS BIT NO. NAME D0 Equalizer Enable D1 Train Inhibit RESET DSP Way D4 Transmit S1 D5 Call Init D6 Special Register Access D7 N CALL TRANSMIT 16 WAY INIT S1 CONDITION DESCRIPTION 0 The adaptive equalizer is in its initialized state ...

Page 15

... TXDALT bit, CR3 bit D7, should have data transitions that start 1/2 bit period delayed from the TXBAUD clock edges. This bit outputs the data received before going to the descrambler. This is useful for sending special unscrambled patterns that can be used for signaling. 15 73K324L Single-Chip Modem D2 D1 TRANSMIT ...

Page 16

... Indicates Device 73K212AL or 73K322L or 73K321L 73K221AL or 73K302L 73K222AL, 73K222BL 73K224L 73K324L 73K224BL 73K324BL Mask in software 16 UNITS BER (default) BER BER BER that are not necessary ...

Page 17

... C 260 C -0.3 to VDD+0.3V CONDITION (VREF to GND) (Placed between VDD and ISET pins) (ISET pin to GND) (VDD to GND) (VDD to GND) Depends on crystal requirements Depends on crystal requirements (11.0592 MHz) Crystal or external clock 17 73K324L Single-Chip Modem MIN NOM MAX UNIT 4.5 5 5.5 0.22 1.8 2 2.2 M 0.22 0.22 22 ...

Page 18

... CCITT V.22bis, V.22, V.21, V.23, Bell 212A Single-Chip Modem DC ELECTRICAL CHARACTERISTICS ( VDD = recommended range unless otherwise noted) PARAMETER IDD, Supply Current IDD1, Active IDD2, Idle Digital Inputs VIL, Input Low Voltage VIH, Input High Voltage All Inputs except Reset XTL1, XTL2 ...

Page 19

... Not in V.21 mode Low Band, ATT = 0100 High Band, ATT = 0100 High-Band to Low-Band Refer to Performance Curves In Call Init mode 460 Hz input signal -70 dBm0 to -30 dBm0 STEP -30 dBm0 to -70 dBm0 STEP @ 460 Hz input signal 19 73K324L Single-Chip Modem MIN NOM MAX UNIT 35 dB -11.5 -10.0 -9 dBm0 - ...

Page 20

... CCITT V.22bis, V.22, V.21, V.23, Bell 212A Single-Chip Modem DYNAMIC CHARACTERISTICS AND TIMING PARAMETERS Carrier Detect Receive Gain Boost “On” for Lower Input Level Measurements Threshold Hysteresis Delay Time FSK DPSK QAM Hold Time FSK DPSK QAM Special Tone Detectors Detect Level ...

Page 21

... Scrambled data at 2400 bit/s in opposite band Sinusoids out of band 1111-0000 Default ATT = 0100 (-10 dBm0) TXA pin; 153.6 kHz Originate or Answer % of data rate originate or answer 550 Hz 1800 Hz 550 Hz 1800 Hz 550 or 1800 Hz 21 73K324L Single-Chip Modem MIN NOM MAX UNIT 200 300 -35 dBm0 -55 dBm0 ...

Page 22

... CCITT V.22bis, V.22, V.21, V.23, Bell 212A Single-Chip Modem DYNAMIC CHARACTERISTICS AND TIMING PARAMETER Timing (Refer to Timing Diagrams) Parallel Mode: TAL TLA TLC TCL TRD TLL TRDF TRW TWW TDW TWD Serial Mode: TRCK TAR TRA TRD TRDF TCKDR TWW TAW TWA TCKDW ...

Page 23

... WRITE TIMING DIAGRAM (SERIAL CONTROL MODE) T2 EXCLK T1 WR A0-A2 TDCK DATA D0 CCITT V.22bis, V.22, V.21, V.23, Bell 212A TLC TRW TCL TLA TRD TRDF READ DATA ADDRESS TCKDR 73K324L Single-Chip Modem TLC TWW TWD TDW WRITE DATA TRDF TCKW TWW TAW TWA ADDRESS TCKDW ...

Page 24

... CCITT V.22bis, V.22, V.21, V.23, Bell 212A Single-Chip Modem APPLICATIONS INFORMATION GENERAL CONSIDERATIONS Figures 1 and 2 show basic circuit diagrams for K-Series modem integrated products are designed to be used in conjunction with a control processor, a UART or RS-232 serial data interface, and a DAA phone line interface to function as a typical intelligent modem ...

Page 25

... D3 2 U1A * - +5V + R10 * IN914 R14 Q 1 10K + 2N2222A C7 C8 0.1 µF 10 µF FIGURE 2: Single 5V Hybrid Version 25 73K324L Single-Chip Modem Because the bottom Semiconductor's 1-chip modem adaptable for use +5V C10 250V R13 22K U2 4N35 VR1 MOV V250L20 R leg ...

Page 26

... CCITT V.22bis, V.22, V.21, V.23, Bell 212A Single-Chip Modem Unlike digital logic circuitry, modem designs must properly contend with precise frequency tolerances and very low level analog signals, to ensure acceptable performance. Using good analog circuit design practices will generally result in a sound design. Following are additional recommendations which should be taken into consideration when starting new designs ...

Page 27

... CCITT V.22bis, V.22, V.21, V.23, Bell 212A 27 73K324L Single-Chip Modem ...

Page 28

... CCITT V.22bis, V.22, V.21, V.23, Bell 212A Single-Chip Modem 28 ...

Page 29

... MECHANICAL SPECIFICATIONS 28-Pin DIP 28-Pin PLCC CCITT V.22bis, V.22, V.21, V.23, Bell 212A 29 73K324L Single-Chip Modem ...

Page 30

... CCITT V.22bis, V.22, V.21, V.23, Bell 212A Single-Chip Modem MECHANICAL SPECIFICATIONS 44-Lead TQFP (continued) 30 ...

Page 31

... ARE THE SAME THE 28-PIN DIP 28-Pin PLCC 73K324L-IH ORDER NO. 73K324L-IP 73K324L-28IH 73K324L-IGT 31 73K324L Single-Chip Modem CAUTION: Use handling procedures necessary for a static sensitive component. 44-Lead TQFP 73K324L-IGT PACKAGE MARK 73K324L-IP 73K324L-28IH 73K324L-IGT 04/24/00- rev. E ...

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