73K324L-IGT ETC [List of Unclassifed Manufacturers], 73K324L-IGT Datasheet - Page 5

• Manufacturer Part Number: 73K324L-IGT
• Description: CCITT V.22bis, V.22, V.21, V.23, Bell 212A Single-Chip Modem
• Manufacturer: ETC [List of Unclassifed Manufacturers]

RS-232 INTERFACE
NAME
EXCLK
RXCLK
RXD
TXCLK
TXD
ANALOG INTERFACE
RXA
TXA
XTL1
XTL2
O/Tristate Receive Clock Tri-statable. The falling edge of this clock output is coincident with
O/Tristate Transmit Clock Tri-statable. This signal is used in synchronous DPSK/QAM
Pull-up
TYPE
Weak
I/O
O/
O
I
I
I
I
DESCRIPTION
External Clock. This signal is used in synchronous transmission when the external
timing option has been selected. In the External Timing mode the rising edge of
EXCLK is used to strobe synchronous transmit data available on the TXD pin. Also
used for serial control interface.
the transitions in the serial received DPSK/QAM data output. The rising edge of
RXCLK can be used to latch the valid output data. RXCLK will be valid as long as
a carrier is present. In V.23 or V.21 mode a clock which is 16 x 1200/75 or 16 x
300 Hz data rate is output, respectively.
Received Data Output. Serial receive data is available on this pin. The data is
always valid on the rising edge of RXCLK when in Synchronous mode. RXD will
output constant marks if no carrier is detected.
transmission to latch serial input data on the TXD pin. Data must be provided so
that valid data is available on the rising edge of the TXCLK. The transmit clock is
derived from different sources depending upon the Synchronization mode
selection. In Internal Mode the clock is generated internally (2400 Hz for QAM,
1200 Hz for DPSK or 600 Hz for half-speed DPSK). In External Mode TXCLK is
phase locked to the EXCLK pin. In Slave Mode TXCLK is phase locked to the
RXCLK pin. TXCLK is always active. In V.23 or V.21 mode the output is a 16 x
1200/75 or 16 x 300 Hz clock, respectively.
Transmit Data Input. Serial data for transmission is input on this pin. In
Synchronous modes, the data must be valid on the rising edge of the TXCLK
clock. In Asynchronous modes (2400/1200/600 bit/s, or 75/300 baud) no clocking
is necessary. DPSK/QAM data must be +1%, -2.5% or +2.3%, -2.5 % in Extended
Overspeed mode.
Received modulated analog signal input from the phone line.
Transmit analog output to the phone line.
These pins are for the internal crystal oscillator requiring a 11.0592 MHz Parallel
mode crystal. Two capacitors from these pins to ground are also required for
proper crystal operation. Consult crystal manufacturer for proper values. XTL2 can
also be driven from an external clock.
CCITT V.22bis, V.22, V.21, V.23, Bell 212A
5
Single-Chip Modem
73K324L