73K324L-IGT ETC [List of Unclassifed Manufacturers], 73K324L-IGT Datasheet - Page 22

• Manufacturer Part Number: 73K324L-IGT
• Description: CCITT V.22bis, V.22, V.21, V.23, Bell 212A Single-Chip Modem
• Manufacturer: ETC [List of Unclassifed Manufacturers]

73K324L
CCITT V.22bis, V.22, V.21, V.23, Bell 212A
Single-Chip Modem
DYNAMIC CHARACTERISTICS AND TIMING
PARAMETER
Timing (Refer to Timing Diagrams)
Parallel Mode:
Serial Mode:
Note:
NOTE: Asserting ALE, CS, and RD or WR concurrently can cause unintentional register accesses. When using
TAL
TLA
TLC
TCL
TRD
TLL
TRDF
TRW
TWW
TDW
TWD
TRCK
TAR
TRA
TRD
TRDF
TCKDR
TWW
TAW
TWA
TCKDW
TCKW
TDCK
T1, T2
T1 and T2 are the low/high periods, respectiv ely, of EXCLK in Serial mode.
non-8031 compatible processors, care must be taken to prevent this from occurring when designing the
interface logic.
CONDITION
CS/Addr. setup before ALE Low
CS/Addr. hold after ALE Low
ALE Low to RD/WR Low
RD/ WR Control to ALE High
Data out from RD Low
ALE width
Data float after RD High
RD width
WR width
Data setup before WR High
Data hold after WR High
Clock high after RD
Address setup before RD low
Address hold after RD low
RD to data valid
Data float after RD high
Read data out after falling edge
of EXCLK
WR width
Address setup before WR
Address hold after rising edge of
WR
Write data hold after falling edge
of EXCLK
WR high after falling edge of
EXCLK
Data setup before falling edge of
EXCLK
Minimum period
(continued)
22
MIN
250
350
350
200
330
500
30
40
10
25
70
70
70
20
50
50
50
6
0
NOM
T1& T2
MAX
110
300
T1
90
40
50
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns