ZL30226/GA ZARLINK [Zarlink Semiconductor Inc], ZL30226/GA Datasheet - Page 112

• Manufacturer Part Number: ZL30226/GA
• Description: 4/8/16 Port IMA/TC PHY Device for xDSL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Address (Hex):
Direct access
Reset Value (Hex):
Address (Hex):
Direct access
Reset Value (Hex):
Address
14:10
Bit #
Offset
09- 17
1B-1F
(Hex)
15
1A
06
07
08
18
19
Type
R/W
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
Unused. Read 0.
Clock source select
These 4 bits are used to select the source for the TXCK for the link when defined as
output:
The valid combinations are:
00000: RXCK0
00010: RXCK2
00100: RXCK4
00110: RXCK6
01000: RXCK8
01010: RXCK10
01100: RXCK12
01110: RXCK14
10000: REFCK0
10010: REFCK2
Byte #
--- ---
14, 13
16, 15
18, 17
48, 19
50, 49
52, 51
---, 53
MSB,
ATM
LSB
0x0600 - 0x060F (16 reg)
1 reg. per TX link.
0000
8 blocks of 32 words (16 bits) from 0x0500 to 0x05FF
Access these locations directly then use transfer command to copy to internal
memory.
These registers need to be initialized for proper operation.
Table 98 - TX IMA ICP Cell Registers (continued)
LSB: Group Status and Control
MSB: Synchronization Information, inserted by the ZL30226/7/8
LSB: Tx Test Control
MSB: Tx Test Pattern
LSB: Rx Test Pattern
MSB: Status and Control of links with LID = 0
Status and Control of links with LID in the range 1-30 (Odd numbered byte in
LSB and even numbered byte in MSB)
LSB: Status and Control of links with LID = 31
MSB: Unused, should be set to 0x6A
LSB: End-to-End channel
MSB: Upper 2 bits of the CRC-10. Inserted by the ZL30226/7/8
LSB: Lower 8 bits of the CRC-10. Inserted by the ZL30226/7/8
MSB: Not used by ZL30226/7/8.
LSB: Not used by ZL30226/7/8.
MSB: Not used by ZL30226/7/8.
Table 99 - TDM TX Link Control Register
Zarlink Semiconductor Inc.
01111: RXCK15
00111: RXCK7
01101: RXCK13
00001: RXCK1
00011: RXCK3
00101: RXCK5
01001: RXCK9
01011: RXCK11
10001: REFCK1
10011: REFCK3
ZL30226/7/8
112
Description
Description
Data Sheet