ZL30226/GA ZARLINK [Zarlink Semiconductor Inc], ZL30226/GA Datasheet - Page 3

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ZL30226/GA

Manufacturer Part Number
ZL30226/GA
Description
4/8/16 Port IMA/TC PHY Device for xDSL
Manufacturer
ZARLINK [Zarlink Semiconductor Inc]
Datasheet
Hardware functions that are implemented in the ZL30226/7/8 device are:
Hardware functions that are implemented by the IMA processor in the ZL30226/7/8 device are:
Utopia Level 1 or 2 compatible MPHY Interface
Incoming HEC verification and correction (optional)
Generation of a new HEC byte
Format outgoing cells into multi-vendor serial TDM formats
Retrieve ATM Cells from the incoming multi-vendor serial TDM format
Perform cell delineation
Cell pre-processing
Provide various counters to assist in performance monitoring
TDM expansion ring to span multiple devices
Transmit scheduler (one per IMA group)
Generation of the TX IMA Data Cell Rate clock
Generation and insertion of ICP cells, Filler Cells and Stuff Cells in IMA mode and Idle Cells in TC mode; the
ICP cells are programmed by the user and the Filler and Idle cells are pre-defined
Perform IMA Frame synchronization
Retrieve and process Rx ICP cells in IMA Mode
Management of RX links to be part of the internal re-sequencer when active
Extraction of RX IMA Data Cell Rate clock
Verification of delays between links
Perform re-sequencing of ATM cells using external asynchronous Static RAM
Can accommodate more than 200 msec of link differential delay depending on the amount of external
memory
Provide structured Interrupt scheme to report various events
Zarlink Semiconductor Inc.
ZL30226/7/8
3
Data Sheet

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