ZL30226/GA ZARLINK [Zarlink Semiconductor Inc], ZL30226/GA Datasheet - Page 98

• Manufacturer Part Number: ZL30226/GA
• Description: 4/8/16 Port IMA/TC PHY Device for xDSL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Note 1: A software global reset of the entire ZL30226/7/8 component can be achieved by simultaneously writing 1s to bits [7:5].
Note 2: Setting bit 8 to a value of 1 requires that bit 0 also be set to a value of 1. See section 6.6.
Address (Hex):
Direct access
Reset Value (Hex):
Address (Hex):
Synchronized access Set address before the transfer is initiated with the RX External SRAM Control
Reset Value (Hex):
Address (Hex):
Synchronized access Set address before the transfer is initiated with the RX External SRAM Control
Reset Value (Hex):
Bit #
Bit #
Bit #
15:9
15:4
15:0
4:3
2:0
3:0
8
7
6
5
Type
Type
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
Unused, Read all 0’s.
Write a 1 for ZL30226/227 memory optimization
Write a 1 to reset the receiver
Write a 1 to reset the transmitter
Write a 1 to reset counters
Write 00 for normal operation.
These 3 bits define the size of the external receive memory:
111: Reserved
110: Reserved
101: 2 banks of 512 K x 8 bits
100: 1 bank of 512 K x 8 bits
011: 2 banks of 128 K x 8 bits
010: 1 bank of 128 K x 8 bits
001: 2 banks of 32 K x 8bits
000: 1 bank of 32 K x 8 bits
RX External SRAM Read/Write Address bit 19:16.
Unused. Read all 0’s.
RX External SRAM Read/Write Address bit 15:0.
0x0299
Defines the external SRAM configuration.
0000
0x0297 (1 reg)
register.
0000
0x0298
register.
0000
Table 67 - RX External SRAM Read/Write Address 1
Table 66 - RX External SRAM Read/Write Address
(1 reg)
(1 reg)
Table 68 - SRAM Control Register
Zarlink Semiconductor Inc.
ZL30226/7/8
1
. Write 0 for normal operation.
1
. 0 means no action.
1
98
. 0 means no action.
Description
Description
Description
2
. 0 means normal operation.
Data Sheet