ZL30226/GA ZARLINK [Zarlink Semiconductor Inc], ZL30226/GA Datasheet - Page 34

• Manufacturer Part Number: ZL30226/GA
• Description: 4/8/16 Port IMA/TC PHY Device for xDSL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

2.0
The transmit path corresponds to a cell flow from the ATM Layer towards the PHY Layer. The ATM cell path on the
transmit side starts at the UTOPIA L2 or L1 Interface. Once ATM cells are received at the UTOPIA port, the device
transfers these cells to the transmit block.
The ZL30226/7/8 provides ATM cell mapping and transmission convergence blocks to transport ATM cells over a
maximum of sixteen flexible serial interface ports. These serial interface ports communicate with most off-the-shelf
xDSL modems/framers or other low speed link devices.
Each of these serial links can be assigned to either an IMA Group or to a TC link. A single serial link cannot be
assigned to more than one IMA Group. The ZL30226 supports up to 4 serial links, while the ZL30227 supports up to
8 serial links and the ZL30228 supports up to 16 serial links.
The functional block diagram (Figure 5) illustrates the transmit function of the ZL30228.
2.1
In general terms, the ZL30226/7/8 transmit input port has the following properties:
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The input port can be enabled to remove (filter) Unassigned or Idle cells. If Unassigned or Idle Cell Filtering is
enabled, the device checks for and discards Unassigned or Idle cells. This function is programmed in the UTOPIA
Input Control (0x0052) register.
Section 5.0 describes the UTOPIA Interface in more detail.
cell level handshaking is compatible with the ATM Forum UTOPIA L1 and L2 Specification
behaves like a UTOPIA compatible MPHY Device or Single PHY Device
each port can be enabled or disabled independently
parity (odd or even) can be checked
optionally verifies and then generates the HEC for incoming cells
includes the ATM Forum polynomial when generating the HEC (default option that can be disabled)
either passes or removes incoming Idle cells
either passes or removes incoming Unassigned cells
provides a counter per UTOPIA port for the total number of Idle/Unassigned/Filler cells with a valid HEC or
optionally the total number of User cells (24 bits/16 bit latched)
provides a counter per UTOPIA port for the total number of cells with wrong incoming HEC (24 bits/16 bit
latched)
provides a counter per UTOPIA port for the total number of cells handled (24 bits/16 bit latched)
provides counters for Parity errors
Cell In Control
The ATM Transmit Path
Zarlink Semiconductor Inc.
ZL30226/7/8
34
Data Sheet