MT90222 ZARLINK [Zarlink Semiconductor Inc], MT90222 Datasheet - Page 139

• Manufacturer Part Number: MT90222
• Description: 4/8/16 Port IMA/TC PHY Device
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

AC Electrical Characteristics - CPU Interface Motorola Timing - Read Cycle
9.1
The CPU Interface of the MT90222/3/4 supports both the Motorola and Intel timing modes. No Mode Select pin is
required.
With Motorola devices, the Motorola R/W-signal is connected to the UP_R/W pin and the UP_OE pin is tied to
ground. There is no DS signal and the UP_CS signal is taken to access the MT90222/3/4.
When used with Intel devices, the READ-signal is connected to the UP_OE pin and the WRITE-signal is connected
to the UP_R/W pin.
When performing a read operation, data is placed on the bus immediately after UP_CS is LOW and UP_R/W is
HIGH for the Motorola timing mode and after the UP_CS and UP_OE signals are LOW for Intel timing.
When performing a write operation in Motorola timing mode, the data is clocked into an MT90222/3/4 pre-load
register on the rising edge of UP_R/W or UP_CS signals. In Intel timing mode, the data is clocked into
MT90222/3/4 pre-load register on the rising edge of the UP_R/W or UP_CS signals. Right after that transition, the
data is transferred to the MT90222/3/4’s internal register. Writing data into this register can take up 2 system clock
cycles.
1
2
3
4
5
R/W set-up time to UP_CS falling edge
Data valid after UP_CS falling edge.
UP_AD or UP_R/W hold time after
UP_CS rising edge
Data hold time after rising edge of
UP_CS
UP_D low impedance after falling edge
of UP_CS
CPU Interface Timing
UP_AD[11:0]
UP_D[15:0]
UP_R/W
UP_OE
UP_CS
Characteristics
(low)
t
ws
Figure 31 - CPU Interface Motorola Timing - Read Access
t
li
Zarlink Semiconductor Inc.
MT90222/3/4
Sym.
t
t
ACC
t
t
WS
t
AH
CH
t
LI
acc
139
Address Valid
Min.
1
4
2
2
Typ.
Data Valid
Max.
35
20
Units
t
ah
ns
ns
ns
ns
ns
Test Conditions
150 pf loads
150 pf loads
Data Sheet
t
ch