MT90222 ZARLINK [Zarlink Semiconductor Inc], MT90222 Datasheet - Page 96
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MT90222
Manufacturer Part Number
MT90222
Description
4/8/16 Port IMA/TC PHY Device
Manufacturer
ZARLINK [Zarlink Semiconductor Inc]
Datasheet
1.MT90222.pdf
(155 pages)
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Address (Hex):
Direct access
Reset Value (Hex):
Address (Hex):
Direct access
Reset Value (Hex):
Address (Hex):
Direct access
Reset Value (Hex):
Bit #
Bit #
Bit #
15:6
13:8
5:2
7:0
1
0
15
14
1
0
Type
Type
Type
R/W
R/W
R/W
R
R
R
R
R
R
R
Table 50 - Processed RX Cell Link FIFO Status Register (continued)
A 1 indicates that the preprocessing FIFO for the link 1 is not empty and it contains
information to be processed by the software.
A 0 indicates that the preprocessing FIFO for the link 1 is empty and does not contain any
new information.
A 1 indicates that the preprocessing FIFO for the link 0 is not empty and it contains
information to be processed by the software.
A 0 indicates that the preprocessing FIFO for the link 0 is empty and does not contain any
new information.
Unused. Always 0.
Reserved. Write 0.
0: Compare entire cell
1: Compare entire ICP cell
0: Global debugging disabled.
1: Global debugging enabled.
A 0 indicates that this word contains the last byte in the RX Cell processed FIFO for the
current link.
A 1 indicates that there is more bytes that were processed.
A 1 indicates that this word contains the last byte from the RX Cell that was processed.
A 0 indicates that there is more bytes that were processed from the same cell.
Cell Offset for the byte found to be different (number range between 1 and 53).
Byte content found to be different from the last received Cell.
0x0107 (1 reg)
1 register for all links.
0000
0x0108
1 register for debug.
0000
0x0140 - 0x014F (16 reg)
1 register per RX Link pre-processed FIFO links.
8000
Table 52 - Processed RX Cell link FIFO Register
Table 51 - ICP Cell RAM DEBUG Register
Zarlink Semiconductor Inc.
MT90222/3/4
96
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Description
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Data Sheet
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