MT90222 ZARLINK [Zarlink Semiconductor Inc], MT90222 Datasheet - Page 142
![no-image](/images/no-image-200.jpg)
MT90222
Manufacturer Part Number
MT90222
Description
4/8/16 Port IMA/TC PHY Device
Manufacturer
ZARLINK [Zarlink Semiconductor Inc]
Datasheet
1.MT90222.pdf
(155 pages)
- Current page: 142 of 155
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Note 1 - For internal synchronization purposes, 2 system clock cycles are required between a write access and the next valid access.
AC Electrical Characteristics - CPU Interface Intel Timing - Write Cycle
1
2
3
4
5
UP_D[15:0]
UP_A[11:0]
UP_R/W
(WRITE)
(READ)
UP_CS set-up time to UP_R/W
falling edge
Address and Data set up before
rising edge of UP_R/W
UP_AD, UP_CS and Data hold
time after UP_R/W rising edge
UP_R/W low after rising edge or
UP_CS
UP_CS high before next UP_CS
low
UP_OE
UP_CS
Characteristics
t
ws
Figure 34 - CPU Interface Intel Timing - Write Access
Sym.
t
t
Zarlink Semiconductor Inc.
t
t
t
ADH
CSH
WS
WH
SU
MT90222/3/4
ADDRESS VALID
DATA VALID
142
(see Note 1)
Min.
t
su
10
1
4
1
2
Typ.
t
adh
Max.
t
csh
t
wh
system
Units
cycle
clock
ns
ns
ns
ns
Conditions
Data Sheet
Test
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