MT90222 ZARLINK [Zarlink Semiconductor Inc], MT90222 Datasheet - Page 62

• Manufacturer Part Number: MT90222
• Description: 4/8/16 Port IMA/TC PHY Device
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

The UTOPIA transmit clock (TxClk) is checked against the system clock. If the incoming byte clock frequency is
lower than 1/128 of the system clock, bit 2 of the General Status (0x040E) register will be set. This bit is cleared by
overwriting it with 0. This aids in debugging as the presence of a UTOPIA clock is required not only for data
transfer but also for proper operation of the UTOPIA registers.
The total space for the UTOPIA input cells for all IMA Groups and links in TC mode is 118. These 118 cells are
shared between 24 TX UTOPIA FIFOs and 16 TX Link FIFOs. The size (length) of each TX UTOPIA FIFO is
defined by writing to the TX IMA Group FIFO Length Definition (0x0093 - 0x0096) registers. The maximum value
is 6 and the minimum value is 0 (in the case the PHY port is not to be used). The size of the TX Link FIFO is defined
on a per group using the TX IMA Control (0x0321-0x0324) registers.
The device will not accept a cell from the UTOPIA Interface if the internal Cell Ram is full. Status bit 0 in the General
Status (0x040E) register is set to 1 to indicate the ’no free cell in TX Cell RAM’ condition. The status bit can be
cleared by overwriting it with 0.
Note that the internal FIFO level on the TX direction is updated after the complete cell is received. If the
corresponding Utopia port address is polled, that the Cell Available Status signal could reflect space available
whereas the FIFO should be reported full. If a cell transfer is initiated under these conditions, the cells will be
accepted and the next time the Utopia port is polled, the Cell Available Status signal will report the correct state of
the FIFOs.
The UTOPIA Input block has the option to verify the HEC of the cell coming from the ATM layer. Four different
options are available and are selected by bits 1 and 0 of the UTOPIA Input Control (0x0052) register.
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5.2
The MT90222/3/4 supports a 53 byte/27 words cell stream via the ATM output port. Cells at the ATM output port are
stored in the RX UTOPIA FIFO before being processed by the UTOPIA Interface. The output of the UTOPIA
Interface can be stopped by the ATM Layer device by de-asserting the RxENB* signal.
The start of a cell is marked with the SOC signal, which is active during the transmission of the first byte/first word
of a cell. The following 52 bytes/26 words are belonging to the same cell.
The RX byte clock (RxClk) can be up to 52 MHz and is checked against the system clock. If the incoming byte clock
frequency is lower than 1/128 of the system clock, bit 3 of the General Status (0x040E) register will be set. This bit
is cleared by overwriting it with 0. This aids in debugging, as the presence of a UTOPIA clock is required not only
for data transfer but also for proper operation of the UTOPIA registers.
The ’00’ option is used to always accept a cell from the ATM layer. The HEC is verified and if wrong, the
UTOPIA Input counter associated with the UTOPIA port for cells with bad HEC is incremented. The
MT90222/3/4 will re-generate a valid HEC based on the content of the 4-byte header that was received.
The ’01’ option is used to verify the HEC of an incoming cell. If the HEC value is wrong and if it can be
corrected (1 bit error), then the cell is corrected and accepted as a good cell. The bad HEC counter is not
incremented if the HEC is corrected. The bad HEC counter is incremented if the HEC value cannot be
corrected. In this mode, the cell is always accepted. The MT90222/3/4 will re-generate a valid HEC based on
the content of the 4-byte header that was received.
The ’10’ option is used to verify the HEC on the incoming cell and discard the cell if the HEC value is wrong.
The bad HEC counter is incremented if a cell is discarded.
The ’11’ option is similar to mode ’01’ except that if the HEC value cannot be corrected, then the cell is
discarded. If the HEC value is corrected, the bad HEC counter is not incremented.
ATM Output Port
Zarlink Semiconductor Inc.
MT90222/3/4
62
Data Sheet