ZL30461MGG ZARLINK [Zarlink Semiconductor Inc], ZL30461MGG Datasheet - Page 15

• Manufacturer Part Number: ZL30461MGG
• Description: COMPACT STRATUM 3 TIMING MODULE
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

1.4.3
The ZL30461 outputs the following clock and frame pulses:
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The combination of two pins, E3DS3/OC3 and E3DS3, controls the selection of different clock configurations (see
Figure 4 “C155o and C34/C44 Clock Generation Options” for details).
C1.5o:
C2o:
C4o:
C6o:
C8o:
C8.5o:
C11o:
C16o:
C19o:
C34o:
C44o:
C155P/N: 155.52 MHz clock with nominal 50% duty cycle
JA19Mo: 19.44 MHz clock with nominal 50% duty cycle
JA77P/N: 77.76 MHz clock with nominal 50% duty cycle
F0o:
F8o:
F16o:
Clock Formats
1.544 MHz clock with nominal 50% duty cycle
2.048 MHz clock with nominal 50% duty cycle
4.096 MHz clock with nominal 50% duty cycle
6.132 MHz clock with nominal 50% duty cycle
8.192 MHz clock with nominal 50% duty cycle
8.592 MHz clock with duty cycle from 30% to 70%
11.184 MHz clock with duty cycle from 30% to 70%
16.384 MHz clock with nominal 50% duty cycle
19.44 MHz clock with nominal 50% duty cycle
34.368 MHz clock with nominal 50% duty cycle
44.736 MHz clock with nominal 50% duty cycle
8 kHz frequency, with 244 ns wide, logic low frame pulse
8 kHz frequency, with 122 ns wide, logic high frame pulse
8 kHz frequency, with 61 ns wide, logic low frame pulse
ZL30461
Output Driver
LVPECL
Driver
Note : Vcc = +3.3V
Figure 3 - LVPECL Output Termination Circuit
Ζ = 50Ω
Ζ = 50Ω
Zarlink Semiconductor Inc.
ZL30461
82.5Ω
127Ω
15
Vcc
82.5Ω
127Ω
LVPECL
Receiver
Data Sheet