ZL30461MGG ZARLINK [Zarlink Semiconductor Inc], ZL30461MGG Datasheet - Page 33
ZL30461MGG
Manufacturer Part Number
ZL30461MGG
Description
COMPACT STRATUM 3 TIMING MODULE
Manufacturer
ZARLINK [Zarlink Semiconductor Inc]
Datasheet
1.ZL30461MGG.pdf
(53 pages)
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The new reference clock will most likely have a different phase, but it may also have a different fractional frequency
offset. To lock to a new reference with a different frequency, the Core PLL will step gradually towards the new
frequency. The frequency slope will be limited to less than 2.0 ppm/sec.
3.1.4
The Normal to Holdover to Normal sequence switching is usually performed when:
•
•
A reference clock is available but its frequency drifts beyond some specified limit. In a Network Element with
Stratum 3 internal clocks, the reference failure is declared when its frequency drifts more than ±12 ppm
beyond its nominal frequency. The ZL30461 indicates this condition by setting PRIOR or SECOR status bits
and pins to logic 1.
During routine maintenance of equipment orderly switching of reference clocks is possible. This may occur
when synchronization references must be rearranged or when a faulty line card must be replaced.
Reference Switching (RefSel): NORMAL --> HOLDOVER --> NORMAL
Figure 9 - Entry into Auto Holdover State and Recovery into Normal Mode by Switching
Reset
_____
Reset == 1
unconditional return from
MS2, MS1 == 10 forces
any state to FreeRun
FreeRun
10
MS2, MS1 != 10
MS2, MS1 == 01 or
RefSel change
Zarlink Semiconductor Inc.
Holdover
ZL30461
01
MS2, MS1 == 00
References
Ref: OK &
33
{Auto}
RefSel change
(Locked)
Normal
(automatic return enabled)
00
AHRD=0
Ref: OK --> Fail &
MS2, MS1 == 00
{Auto}
Holdover
Auto
Ref: Fail --> OK &
MS2, MS1 == 00
& AHRD=1 &
MHR 0 --> 1
{Manual}
Ref: Fail --> OK &
MS2, MS1 == 00
& AHRD=0 &
{Auto}
Data Sheet
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