ZL30461MGG ZARLINK [Zarlink Semiconductor Inc], ZL30461MGG Datasheet - Page 27

• Manufacturer Part Number: ZL30461MGG
• Description: COMPACT STRATUM 3 TIMING MODULE
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Address: 13 H
Address: 14 H
7-6
7-5
Bit
Bit
5
4
3
2
1
0
4
3
2
1
0
C16odis
C19odis
F16odis
C1.5dis
C8odis
C4odis
C6odis
F8odis
F0odis
Name
Name
C2dis
RSV
RSV
RSV
Reserved.
C16o (16.384 MHz) Clock Disable. When set to 1, this bit tristates the
16.384 MHz clock output.
C8o (8.192 MHz) Clock Disable. When set to 1, this bit tristates the 8.192 MHz
clock output.
C4o (4.096 MHz) Clock Disable. When set to 1, this bit tristates the 4.096 MHz
clock output.
C2o (2.048 MHz) Clock Disable. When set to 1, this bit tristates the 2.048 MHz
clock output.
C1.5o (1.544 MHz) Clock Disable. When set to 1, this bit tristates the
1.544 MHz clock output.
Reserved.
Reserved.
F8o Frame Pulse Disable. When set to 1, this bit tristates the 8 kHz 244 ns
active high framing pulse output.
F0o Frame Pulse Disable. When set to 1, this bit tristates the 8 kHz 122 ns
active low framing pulse output.
F16o Frame Pulse Disable. When set to 1, this bit tristates the 8 kHz 61 ns
active low framing pulse output.
C6o (6.312 MHz) Clock Disable. When set to 1, this bit tristates the 6.312 MHz
clock output.
C19o (19.44 MHz) Clock Disable. When set to 1, this bit tristates the
19.44 MHz clock output.
Table 13 - Clock Disable Register 1 (R/W)
Table 14 - Clock Disable Register 2 (R/W)
Zarlink Semiconductor Inc.
Functional Description
Functional Description
ZL30461
27
Data Sheet
Default
Default
000
00
0
0
0
0
0
0
0
0
0
0
0