ZL50020GAC ZARLINK [Zarlink Semiconductor Inc], ZL50020GAC Datasheet - Page 41
![no-image](/images/no-image-200.jpg)
ZL50020GAC
Manufacturer Part Number
ZL50020GAC
Description
Enhanced 2 K Digital Switch
Manufacturer
ZARLINK [Zarlink Semiconductor Inc]
Datasheet
1.ZL50020GAC.pdf
(83 pages)
- Current page: 41 of 83
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15 - 9
External Read/Write Address: 0001
Reset Value: 0000
Bit
8
7
6
5
4
15
0
14
0
STIO_PD_
RBEREN
TBEREN
Unused
Name
BDH
BDL
EN
H
13
0
12
0
Reserved. In normal functional mode, these bits MUST be set to zero.
STio Pull-down Enable
When this bit is low, the pull-down resistors on all STio pads will be disabled.
When this bit is high, the pull-down resistors on all STio pads will be enabled.
Bi-directional Control for Streams 16-31
Bi-directional Control for Streams 0-15
PRBS Receiver Enable
When this bit is low, all the BER receivers are disabled. To enable any BER receivers,
this bit MUST be high.
PRBS Transmitter Enable
When this bit is low, all the BER transmitters are disabled. To enable any BER
transmitters, this bit MUST be high.
Table 14 - Internal Mode Selection Register (IMS) Bits
11
0
H
10
0
9
0
Zarlink Semiconductor Inc.
PD_EN
STIO_
BDH
BDL
0
1
0
1
8
ZL50020
41
BDH
7
STio16-31 are bi-directional
STi16-31 tied low internally
STio0-15 are bi-directional
STi0-15 tied low internally
bi-directional operation:
bi-directional operation:
STio16 - 31 Operation
STio16-31 are outputs
STio0 - 15 Operation
STio0-15 are outputs
STi16-31 are inputs
STi0-15 are inputs
normal operation:
normal operation:
Description
BDL
6
RBER
EN
5
TBER
EN
4
BPD
3
2
BPD
2
1
BPD
1
0
Data Sheet
MBPS
0
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