ZL50020GAC ZARLINK [Zarlink Semiconductor Inc], ZL50020GAC Datasheet - Page 75
ZL50020GAC
Manufacturer Part Number
ZL50020GAC
Description
Enhanced 2 K Digital Switch
Manufacturer
ZARLINK [Zarlink Semiconductor Inc]
Datasheet
1.ZL50020GAC.pdf
(83 pages)
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† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C, VDD_CORE at 1.8 V and VDD_IO at 3.3 V and are for design aid only: not guaranteed and not subject to produc-
tion testing.
AC Electrical Characteristics
1
2
Input and Output Frame Offset in
Divided Clock Mode
Input and Output Frame Offset in
Multiplied Clock Mode
(16.384 MHz)
Input Frame Boundary
(4.096 MHz)
(8.192 MHz)
(4.096 MHz)
CKi
CKi
CKo0
FPi
CKi
FPi
FPo0
FPi
Characteristic
Figure 35 - Input and Output Frame Boundary Offset
†
- Clock Mode Input/Output Frame Boundary Alignment
t
FBOS
Zarlink Semiconductor Inc.
Sym.
t FBOS
t FBOS
Output Frame Boundary
ZL50020
75
Min.
5
2
Typ.
‡
Max.
13
10
Units
ns
ns
Input reference jitter is
equal to zero.
Notes
Data Sheet
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