ZL50020GAC ZARLINK [Zarlink Semiconductor Inc], ZL50020GAC Datasheet - Page 69
![no-image](/images/no-image-200.jpg)
ZL50020GAC
Manufacturer Part Number
ZL50020GAC
Description
Enhanced 2 K Digital Switch
Manufacturer
ZARLINK [Zarlink Semiconductor Inc]
Datasheet
1.ZL50020GAC.pdf
(83 pages)
- Current page: 69 of 83
- Download datasheet (683Kb)
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C, VDD_CORE at 1.8 V and VDD_IO at 3.3 V and are for design aid only: not guaranteed and not subject to produc-
tion testing.
AC Electrical Characteristics
Input Frame Boundary
1
2
3
4
5
6
7
8
FPi Input Frame Pulse Width
FPi Input Frame Pulse Setup Time
FPi Input Frame Pulse Hold Time
CKi Input Clock Period
CKi Input Clock High Time
CKi Input Clock Low Time
CKi Input Clock Rise/Fall Time
CKi Input Clock Cycle to Cycle Variation
Input Frame Boundary
Figure 26 - Frame Pulse Input and Clock Input Timing Diagram (GCI-Bus)
Figure 25 - Frame Pulse Input and Clock Input Timing Diagram (ST-BUS)
FPi
CKi
FPi
CKi
Characteristic
†
- FPi and CKi Timing when CKIN1-0 bits = 10 (4.096 MHz)
t
t
FPIS
FPIS
t
t
FPIW
FPIW
Zarlink Semiconductor Inc.
ZL50020
t
t
FPIH
FPIH
69
t
r
CKi, t
t
t
Sym.
t
t
t
t
t
t
rCKI
rCKI
t
FPIW
CKIH
FPIS
FPIH
CKIP
CKIL
CVC
t
t
CKIH
CKIH
f
CKi
t
t
CKIP
CKIP
Min.
220
110
110
110
110
90
0
t
t
fCKI
fCKI
t
t
CKIL
CKIL
Typ.
244
244
‡
Max. Units Notes
420
270
135
135
20
3
Data Sheet
ns
ns
ns
ns
ns
ns
ns
ns
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