ZL50020GAC ZARLINK [Zarlink Semiconductor Inc], ZL50020GAC Datasheet - Page 74

• Manufacturer Part Number: ZL50020GAC
• Description: Enhanced 2 K Digital Switch
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C, VDD_CORE at 1.8 V and VDD_IO at 3.3 V and are for design aid only: not guaranteed and not subject to produc-
tion testing.
Note 1:
AC Electrical Characteristics
1
2
3
STio Delay - Active to High-Z
STio Delay - High-Z to Active
Output Drive Enable (ODE) Delay
- High-Z to Active
ODE
STio
High impedance is measured by pulling to the appropriate rail with R
discharge C
CKi @ 4.096 MHz
CKi @ 8.192 MHz
CKi @ 16.384 MHz
Characteristic
t
L
ZD_ODE
.
HiZ
†
CKo0
- ST-BUS/GCI-Bus Output Tristate Timing
FPo0
STio
STio
Figure 33 - Serial Output and External Control
Figure 34 - Output Drive Enable (ODE)
Valid Data
t
ZD_ODE
Sym.
t
t
Zarlink Semiconductor Inc.
DZ
ZD
Valid Data
ZL50020
Tristate
t
DZ_ODE
Min.
74
-3
-8
-3
-8
t
t
DZ
ZD
Typ.
V
CT
L
Valid Data
Tristate
, with timing corrected to cancel the time taken to
‡
V
HiZ
CT
Max.
260
138
77
77
7
0
7
0
V
V
CT
CT
Units
ns
ns
ns
ns
ns
ns
ns
ns
Multiplied Clock Mode
Divided Clock Mode
Multiplied Clock Mode
Divided Clock Mode
Multiplied Clock Mode
Divided Clock Mode
Test Conditions
Data Sheet
V
V
CT
CT
*